| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| wedge100_syscpld_top_inst|heart_attack_inst|heart_pos_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|heart_attack_inst|clk_10hz_pos_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|heart_attack_inst |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|led_if_u|led_sr_if_inst |
9 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|led_if_u|led_blink_pos_edge |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|led_if_u|led_0_start_pos_edge |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|led_if_u|led_selection_inst|pb_in_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|led_if_u|led_selection_inst |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|led_if_u |
53 |
6 |
30 |
6 |
20 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|uart_mux_u |
19 |
1 |
8 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|irq_ctrl_inst |
90 |
41 |
21 |
41 |
75 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_1_SLAVE|CNT_SCL|LPM_COUNTER_component|auto_generated |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_1_SLAVE|CNT_SCL |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_1_SLAVE|TX_BUF |
12 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_1_SLAVE|RX_BUF |
4 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_1_SLAVE |
12 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_0_SLAVE|CNT_SCL|LPM_COUNTER_component|auto_generated |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_0_SLAVE|CNT_SCL |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_0_SLAVE|TX_BUF |
12 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_0_SLAVE|RX_BUF |
4 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|I2C_0_SLAVE |
12 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|reg_file_inst |
321 |
35 |
1 |
35 |
305 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_reason_u|pd_main_positive_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_reason_u|pd_stby_positive_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_reason_u|reset_hot_n_positive_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_reason_u|reset_warm_n_positive_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_reason_u|reset_cold_n_positive_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_reason_u |
20 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_out_u |
82 |
0 |
18 |
0 |
57 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_ctrl_u |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|sw_hot_pos_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|sw_warm_pos_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|sw_cold_pos_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|sw_pwr_pos_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|wdt_2_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|wdt_1_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|bmc_cpld_reset_4_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|bmc_cpld_reset_3_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|bmc_cpld_reset_2_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|bmc_cpld_reset_1_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|bmc_req_reset_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|facebook_reset_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|pb_dbg_reset_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u|pb_reset_neg_edge |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u|reset_trigger_u |
31 |
0 |
5 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|system_boot_u |
117 |
8 |
3 |
8 |
92 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|f1hz |
29 |
28 |
0 |
28 |
1 |
28 |
28 |
28 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst|f10hz |
29 |
28 |
0 |
28 |
1 |
28 |
28 |
28 |
0 |
0 |
0 |
0 |
0 |
| wedge100_syscpld_top_inst |
85 |
1 |
1 |
1 |
104 |
1 |
1 |
1 |
11 |
0 |
0 |
0 |
0 |