| Figure 93: Example SMBus Connections | = | Figure 93: Example SMBus Connections |
| NC-SI over RBT Interface Pins | NC-SI over RBT Interface Pins | |
| This section provides the pin assignments for the NC-SI over RBT interface signals on the Primary Connector OCP bay. The AC/DC specifications for NC-SI over RBT are defined in the DMTF DSP0222 NC-SI specification. Example connection diagrams are shown in Figure 94 and Figure 95. | This section provides the pin assignments for the NC-SI over RBT interface signals on the Primary Connector OCP bay. The AC/DC specifications for NC-SI over RBT are defined in the DMTF DSP0222 NC-SI specification. Example connection diagrams are shown in Figure 94 and Figure 95. | |
| The baseboard shall possess the ability to isolate the RBT pins, including RBT_CLK_IN. The isolation logic shall be controlled with a baseboard generated signal called RBT_ISOLATE#. This signal is not pinned out on the Primary or Secondary Connectors. RBT_ISOLATE# shall be low when AUX_PWR_EN=0 or before the card side supplies have been fully enabled (AUX_PWR_EN=1 and NIC_PWR_GOOD=0). RBT_ISOLATE# shall be high when AUX_PWR_EN=1 and the first rising edge of NIC_PWR_GOOD=1 (upon entering Aux Power Mode). RBT_ISOLATE# shall remain high during the transition to Main Power Mode when the NIC_PWR_GOOD signal is in the don’t care state. RBT_ISOLATE# shall be high when (AUX_PWR_EN=1, MAIN_PWR_EN=1 and NIC_PWR_GOOD=1). e truth table that describes the RBT_ISOLATE# behavior Table 26 and shown in | <> | The baseboard shall possess the ability to isolate the RBT pins, including RBT_CLK_IN. The isolation logic shall be controlled with a baseboard generated signal called RBT_ISOLATE#. This signal is not pinned out on the Primary or Secondary Connectors. RBT_ISOLATE# shall be low when AUX_PWR_EN=0 or before the card side supplies have been fully enabled (AUX_PWR_EN=1 and NIC_PWR_GOOD=0). RBT_ISOLATE# shall become high when AUX_PWR_EN=1 and the rising edge of NIC_PWR_GOOD=1 (upon entering Aux Power Mode). RBT_ISOLATE# shall remain high during the transition to Main Power Mode when the NIC_PWR_GOOD signal is in the don’t care state. RBT_ISOLATE# shall be high when (AUX_PWR_EN=1, MAIN_PWR_EN=1 and NIC_PWR_GOOD=1). e truth table that describes the RBT_ISOLATE# behavior Table 26 and shown in |
| = | ||
| Table 26: RBT_ISOLATE# Truth Table | Table 26: RBT_ISOLATE# Truth Table | |
| AUX_PWR_EN | AUX_PWR_EN | |
| MAIN_PWR_EN | MAIN_PWR_EN | |
| NIC_PWR_GOOD | NIC_PWR_GOOD | |
| 1 | = | 1 |
| X | X | |
| Rising edge on entering Aux Power Mode | Rising edge on entering Aux Power Mode | |
| 1 | 1 | |
| 1 | 1 | |
| 1 | 1 | |
| Don’t care state | <> | |
| 1 | X | |
| 1 | ||
| 1 | ||
| 1 | ||
| 1 | = | 1 |
| Isolation prevents a leakage path through unpowered silicon. Example buffering implementations are shown in Figure 94 and Figure 95. | Isolation prevents a leakage path through unpowered silicon. Example buffering implementations are shown in Figure 94 and Figure 95. | |
| RBT reference clock buffers are permitted on the OCP NIC for multi-endpoint implementations if the NIC timing budget is not violated. Refer to the signal integrity requirements in Section 5.1 for timing budget details. | RBT reference clock buffers are permitted on the OCP NIC for multi-endpoint implementations if the NIC timing budget is not violated. Refer to the signal integrity requirements in Section 5.1 for timing budget details. | |
| Signal Description | = | Signal Description |
| RBT_CLK_IN | RBT_CLK_IN | |
| OCP_A14 | OCP_A14 | |
| Output | Output | |
| Reference clock input. Synchronous clock reference for receive, transmit and control interface. The clock shall have a typical frequency of 50MHz ±50 ppm. | Reference clock input. Synchronous clock reference for receive, transmit and control interface. The clock shall have a typical frequency of 50MHz ±50 ppm. | |
| For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the Primary Connector OCP bay. The RBT_CLK_IN shall not be driven until the card has transitioned into Aux Power Mode. The RBT_CLK_IN shall be continuous once it has started. | <> | For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the Primary Connector OCP bay. The RBT_CLK_IN shall not be driven until the card has transitioned into Aux Power Mode. The RBT_CLK_IN shall be continuous once it has started and while RBT_ISOLATE# is high. |
| = | ||
| If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to ground through a 100 kΩ pull down resistor. | If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to ground through a 100 kΩ pull down resistor. | |
| For OCP NIC 3.0 cards, this pin shall be connected between the card gold finger and the endpoint silicon. This pin shall be left as a no connect if NC-SI over RBT is not supported. | For OCP NIC 3.0 cards, this pin shall be connected between the card gold finger and the endpoint silicon. This pin shall be left as a no connect if NC-SI over RBT is not supported. | |
| RBT_CRS_DV | RBT_CRS_DV | |
| OCP_B14 | OCP_B14 | |
| M | = | M |
| M | M | |
| M = Mandatory. Function is required in the designated power state.O = Optional. Function is optionally supported in the designated power state. | M = Mandatory. Function is required in the designated power state.O = Optional. Function is optionally supported in the designated power state. | |
| Note 1: Only the PRSNTB[3:0]# scan chain signals are valid in ID mode as the OCP NIC 3.0 card power rails have not yet been enabled via the AUX_PWR_EN/MAIN_PWR_EN signals. | Note 1: Only the PRSNTB[3:0]# scan chain signals are valid in ID mode as the OCP NIC 3.0 card power rails have not yet been enabled via the AUX_PWR_EN/MAIN_PWR_EN signals. | |
| Note 2: The +12V_EDGE rail may be disabled at this time, but the max permissible leakage is up to the ID Mode / Programming Mode current limit defined in Section 3.9. | <> | Note 2: The +12V_EDGE rail is optionally disabled by the baseboard during this power state. The max permissible leakage is up to the ID Mode / Programming Mode current limit defined in Section 3.9. The NIC shall not rely on +12V_EDGE power in this state and shall not malfunction if +12V_EDGE is present or absent. |
| = | ||
| Note 3: The +12V_EDGE rail is on, but the max permissible current draw is up to the Aux Power Mode current limit defined in Section 3.9. | <> | Note 3: The +12V_EDGE rail is on. The max permissible current draw is up to the Aux Power Mode current limit defined in Section 3.9. |
| = | ||
| Note 4: The FRU EEPROM WP pin is low (not write protected) to enable programming using any of the defined methods for controlling the EEPROM WP signal. Refer to the FRU Write Protection Mechanism field in Section 4.10.3. | Note 4: The FRU EEPROM WP pin is low (not write protected) to enable programming using any of the defined methods for controlling the EEPROM WP signal. Refer to the FRU Write Protection Mechanism field in Section 4.10.3. | |
| NIC Power Off | NIC Power Off | |
| In NIC Power Off mode, all power delivery has been turned off or the card is not physically plugged into the baseboard. Transition to this state can be from any other state. | In NIC Power Off mode, all power delivery has been turned off or the card is not physically plugged into the baseboard. Transition to this state can be from any other state. | |
| ID Mode | ID Mode | |
| In the ID Mode, only +3.3V_EDGE is available for powering up the FRU EEPROM and the Scan Chain devices. All OCP NIC 3.0 cards must enter the ID Mode state for FRU EEPROM and scan chain queries immediately following the NIC Power Off state. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0. | In the ID Mode, only +3.3V_EDGE is available for powering up the FRU EEPROM and the Scan Chain devices. All OCP NIC 3.0 cards must enter the ID Mode state for FRU EEPROM and scan chain queries immediately following the NIC Power Off state. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0. | |
| Minimum time between AUX_PWR_EN deassertion to AUX_PWR_EN reassertion for LFF cards. Delay time allows for OCP NIC 3.0 card capacitors to discharge and prevent reapplying power into a pre-biased condition. | = | Minimum time between AUX_PWR_EN deassertion to AUX_PWR_EN reassertion for LFF cards. Delay time allows for OCP NIC 3.0 card capacitors to discharge and prevent reapplying power into a pre-biased condition. |
| Digital I/O Specifications | Digital I/O Specifications | |
| All digital I/O pins on the connector boundary are +3.3 V signaling levels. The following tables provide the absolute max levels. Refer to the appropriate specifications for the RBT, PCIe and SMBus DC/AC specifications for any superseded values. | <> | This section is for informative reference only. All digital I/O pins on the connector boundary are +3.3 V signaling levels. The following tables provide the absolute max levels. Refer to the appropriate specifications for the RBT, PCIe and SMBus DC/AC specifications for any superseded values. |
| = | ||
| Table 45: Digital I/O DC specifications | Table 45: Digital I/O DC specifications | |
| Symbol | Symbol | |
| Parameter | Parameter | |
| Min | Min | |
| Max | Max | |
| VOL | = | VOL |
| Output low voltage | Output low voltage | |
| 0.8 | 0.8 | |
| V | V | |
| IOH | <> | |
| Output high current | ||
| = | ||
| mA | <> | |
| = | ||
| IOH | <> | |
| Output low current | ||
| = | ||
| mA | <> | |
| = | ||
| VIH1 | VIH1 | |
| Input voltage | Input voltage | |
| 2.0 | 2.0 | |
| 3.6 | 3.6 | |
| V | V | |
| VIL2 | = | VIL2 |
| Input low voltage | Input low voltage | |
| - | - | |
| 1.0 | 1.0 | |
| V | V | |
| 5 | 5 | |
| IOH | <> | |
| Input current | ||
| = | ||
| mA | <> | |
| = | ||
| Table 46: Digital I/O AC specifications | Table 46: Digital I/O AC specifications | |
| Symbol | Symbol | |
| Parameter | Parameter | |
| Min | Min | |