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2 Version 1.1.0 <> 2 Version 1.2.0
 
5 1        Overview        10 <> 5 1        Overview        11
6 1.1        License        10   6 1.1        License        11
7 1.2        Acknowledgements        11   7 1.2        Acknowledgements        12
8 1.3        References        12   8 1.3        References        13
9 1.3.1        Trademarks        13   9 1.3.1        Trademarks        14
10 1.4        Acronyms        14   10 1.4        Acronyms        15
11 1.5        Conventions        15   11 1.5        Conventions        16
12 1.6        Background        16   12 1.6        Background        18
13 1.7        Overview        18   13 1.7        Overview        21
14 1.7.1        Mechanical Form Factor Overview        18   14 1.7.1        Mechanical Form Factor Overview        21
15 1.7.2        Electrical Overview        20   15 1.7.2        Electrical Overview        23
16 1.7.2.1        Primary Connector        20   16 1.7.2.1        Primary Connector        23
17 1.7.2.2        Secondary Connector        21   17 1.7.2.2        Secondary Connector        24
18 1.8        Non-NIC Use Cases        21   18 1.8        Non-NIC Use Cases        24
19 2        Mechanical Card Form Factor        22   19 2        Mechanical Card Form Factor        25
20 2.1        Form Factor Options        22   20 2.1        Form Factor Options        25
21 2.1.1        SFF Faceplate Configurations        24   21 2.1.1        SFF and TSFF Faceplate Configurations        27
22 2.1.2        LFF Faceplate Configurations        28   22 2.1.2        LFF Faceplate Configurations        31
23 2.2        Line Side I/O Implementations        32   23 2.2        Line Side I/O Implementations        35
24 2.3        Top Level Assembly (SFF and LFF)        33   24 2.3        Top Level Assembly (SFF, TSFF and LFF)        36
25 2.4        Faceplate Subassembly (SFF and LFF)        34   25 2.4        Faceplate Subassembly (SFF, TSFF and LFF)        38
26 2.4.1        Faceplate Subassembly – Exploded View        34   26 2.4.1        Faceplate Subassembly – Exploded View        38
27 2.4.2        Faceplate Subassembly – Bill of Materials (BOM)        34   27 2.4.2        Faceplate Subassembly – Bill of Materials (BOM)        38
28 2.4.3        SFF Generic I/O Faceplate        37   28 2.4.3        SFF Generic I/O Faceplates        41
      29 2.4.4        TSFF Generic I/O Faceplates        42
29 2.4.4        LFF Generic I/O Faceplate        38   30 2.4.5        LFF Generic I/O Faceplate        44
30 2.4.5        Ejector Lever (SFF)        39   31 2.4.6        Ejector Lever (SFF, TSFF)        45
31 2.4.6        Ejector Levers (LFF)        40   32 2.4.7        Ejector Levers (LFF)        46
32 2.4.7        Ejector Lock (SFF and LFF)        41   33 2.4.8        Ejector Lock (SFF, TSFF and LFF)        47
33 2.4.8        Clinch Nut (SFF and LFF)        42   34 2.4.9        Clinch Nut (SFF and LFF)        48
34 2.5        Card Keep Out Zones        43   35 2.5        Card Keep Out Zones        49
35 2.5.1        SFF Keep Out Zones        43   36 2.5.1        SFF Keep Out Zones        49
      37 2.5.2        TSFF Keep Out Zones        52
36 2.5.2        LFF Keep Out Zones        46   38 2.5.3        LFF Keep Out Zones        53
37 2.6        Baseboard Keep Out Zones        49   39 2.6        Baseboard Keep Out Zones        56
38 2.7        Insulation Requirements        50   40 2.7        Insulation Requirements        57
39 2.7.1        SFF Insulator        50   41 2.7.1        SFF, TSFF Insulator        57
40 2.7.2        LFF Insulator        52   42 2.7.2        LFF Insulator        59
41 2.8        Critical-to-Function (CTF) Dimensions (SFF and LFF)        55   43 2.8        Critical-to-Function (CTF) Dimensions (SFF, TSFF and LFF)        62
42 2.8.1        CTF Tolerances        55   44 2.8.1        CTF Tolerances        62
43 2.8.2        SFF Pull Tab CTF Dimensions        55   45 2.8.2        SFF Pull Tab CTF Dimensions        62
44 2.8.3        SFF Ejector Latch CTF Dimensions        57   46 2.8.3        SFF Ejector Latch CTF Dimensions        64
45 2.8.4        SFF Internal Lock CTF Dimensions        58   47 2.8.4        SFF Internal Lock CTF Dimensions        65
46 2.8.5        SFF Baseboard CTF Dimensions        59   48 2.8.5        SFF Baseboard CTF Dimensions        66
      49 2.8.6        TSFF Pull Tab CTF Dimensions        69
      50 2.8.7        TSFF Ejector Latch CTF Dimensions        69
      51 2.8.8        TSFF Internal Lock CTF Dimensions        69
      52 2.8.9        TSFF Baseboard CTF Dimensions        69
47 2.8.6        LFF Ejector Latch CTF Dimensions        62   53 2.8.10        LFF Ejector Latch CTF Dimensions        69
48 2.8.7        LFF Baseboard CTF Dimensions        63   54 2.8.11        LFF Baseboard CTF Dimensions        71
49 2.9        Labeling Requirements        66   55 2.9        Labeling Requirements        74
50 2.9.1        General Guidelines for Label Contents        66   56 2.9.1        General Guidelines for Label Contents        74
51 2.9.2        MAC Address Labeling Requirements        67   57 2.9.2        MAC Address Labeling Requirements        75
52 2.9.2.1        MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        68   58 2.9.2.1        MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        76
53 2.9.2.2        MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controllers        68   59 2.9.2.2        MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controllers        76
54 2.9.2.3        MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers        69   60 2.9.2.3        MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers        77
55 2.9.2.4        MAC Address Label Example 4 – Singe Port with Quad Host, Single Managed Controller        69   61 2.9.2.4        MAC Address Label Example 4 – Singe Port with Quad Host, Single Managed Controller        77
56 2.10        Mechanical CAD Package Examples        71   62 2.10        Mechanical CAD Package Examples        79
57 3        Electrical Interface Definition – Card Edge and Baseboard        72   63 3        Electrical Interface Definition – Card Edge and Baseboard        80
58 3.1        Card Edge Gold Finger Requirements        72   64 3.1        Card Edge Gold Finger Requirements        80
59 3.1.1        Gold Finger Mating Sequence        74   65 3.1.1        Gold Finger Mating Sequence        82
60 3.2        Baseboard Connector Requirements        78   66 3.2        Baseboard Connector Requirements        86
61 3.2.1        Right Angle Connector        78   67 3.2.1        Right Angle Connector        86
62 3.2.2        Right Angle Offset        79   68 3.2.2        Right Angle Offset        87
63 3.2.3        Straddle Mount Connector        79   69 3.2.3        Straddle Mount Connector        87
64 3.2.4        Straddle Mount Offset and PCB Thickness Options        81   70 3.2.4        Straddle Mount Offset and PCB Thickness Options        89
65 3.2.5        LFF Connector Locations        82   71 3.2.5        LFF Connector Locations        90
66 3.3        Pin Definition        82   72 3.3        Pin Definition        90
67 3.3.1        Primary Connector        83   73 3.3.1        Primary Connector        91
68 3.3.2        Secondary Connector        85   74 3.3.2        Secondary Connector        93
69 3.4        Signal Descriptions        86   75 3.4        Signal Descriptions        94
70 3.4.1        PCIe Interface Pins        86   76 3.4.1        PCIe Interface Pins        94
71 3.4.2        PCIe Present and Bifurcation Control Pins        92   77 3.4.2        PCIe Present and Bifurcation Control Pins        101
72 3.4.3        SMBus Interface Pins        95   78 3.4.3        SMBus Interface Pins        104
73 3.4.4        NC-SI over RBT Interface Pins        96   79 3.4.4        NC-SI over RBT Interface Pins        105
74 3.4.5        Scan Chain Pins        104   80 3.4.5        Scan Chain Pins        113
75 3.4.6        Power Supply Pins        113   81 3.4.6        Power Supply Pins        122
76 3.4.7        USB 2.0 (A68/A69) – Primary Connector Only        118   82 3.4.7        USB 2.0 (A68/A69) – Primary Connector Only        127
77 3.4.8        UART (A68/A69) – Secondary Connector Only        120   83 3.4.8        UART (A68/A69) – Secondary Connector Only        129
78 3.4.9        RFU[1:4] Pins        122   84 3.4.9        RFU[1:4] Pins        130
79 3.5        PCIe Bifurcation Mechanism        123   85 3.5        PCIe Bifurcation Mechanism        131
80 3.5.1        PCIe OCP NIC 3.0 Card to Baseboard Bifurcation Configuration (PRSNTA#, PRSNTB[3:0]#)        123   86 3.5.1        PCIe OCP NIC 3.0 Card to Baseboard Bifurcation Configuration (PRSNTA#, PRSNTB[3:0]#)        131
81 3.5.2        PCIe Baseboard to OCP NIC 3.0 Card Bifurcation Configuration (BIF[2:0]#)        123   87 3.5.2        PCIe Baseboard to OCP NIC 3.0 Card Bifurcation Configuration (BIF[2:0]#)        131
82 3.5.3        PCIe Bifurcation Decoder        124   88 3.5.3        PCIe Bifurcation Decoder        132
83 3.5.4        Bifurcation Detection Flow        126   89 3.5.4        Bifurcation Detection Flow        134
84 3.5.5        PCIe Bifurcation Examples        127   90 3.5.5        PCIe Bifurcation Examples        135
85 3.5.5.1        Single Host (1 x16) Baseboard with a 1 x16 OCP NIC 3.0 Card (Single Controller)        127   91 3.5.5.1        Single Host (1 x16) Baseboard with a 1 x16 OCP NIC 3.0 Card (Single Controller)        135
86 3.5.5.2        Single Host (2 x8) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controllers)        128   92 3.5.5.2        Single Host (2 x8) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controllers)        136
87 3.5.5.3        Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Single Controller)        129   93 3.5.5.3        Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Single Controller)        137
88 3.5.5.4        Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Quad Controllers)        130   94 3.5.5.4        Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Quad Controllers)        138
89 3.5.5.5        Single Host (1 x16, no Bifurcation) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controller)        131   95 3.5.5.5        Single Host (1 x16, no Bifurcation) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controller)        139
90 3.6        PCIe REFCLK and PERST# Mapping        132   96 3.6        PCIe REFCLK and PERST# Mapping        140
91 3.6.1        SFF PCIe REFCLK and PERST# Mapping        133   97 3.6.1        SFF, TSFF PCIe REFCLK and PERST# Mapping        141
92 3.6.2        LFF PCIe REFCLK and PERST# Mapping        136   98 3.6.2        LFF PCIe REFCLK and PERST# Mapping        144
93 3.6.3        REFCLK and PERST# Mapping Expansion        138   99 3.6.3        REFCLK and PERST# Mapping Expansion        146
94 3.7        Port Numbering and LED Implementations        139   100 3.7        Port Numbering and LED Implementations        147
95 3.7.1        OCP NIC 3.0 Port Naming and Port Numbering        139   101 3.7.1        OCP NIC 3.0 Port Naming and Port Numbering        147
96 3.7.2        OCP NIC 3.0 Card LED Configuration        139   102 3.7.2        OCP NIC 3.0 Card LED Configuration        147
97 3.7.3        OCP NIC 3.0 Card LED Ordering        141   103 3.7.3        OCP NIC 3.0 Card LED Ordering        149
98 3.7.4        Baseboard LEDs Configuration over the Scan Chain        142   104 3.7.4        Baseboard LEDs Configuration over the Scan Chain        150
99 3.8        Power State Machine        144   105 3.8        Power State Machine        152
100 3.8.1        NIC Power Off        145   106 3.8.1        NIC Power Off        153
101 3.8.2        ID Mode        145   107 3.8.2        ID Mode        153
102 3.8.3        Aux Power Mode        146   108 3.8.3        Aux Power Mode        154
103 3.8.4        Main Power Mode        146   109 3.8.4        Main Power Mode        154
104 3.8.5        Programming Mode        146   110 3.8.5        Programming Mode        154
105 3.9        Power Supply Rail Requirements and Slot Power Envelopes        147   111 3.9        Power Supply Rail Requirements and Slot Power Envelopes        155
106 3.10        Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails        148   112 3.10        Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails        156
107 3.11        Power Sequence Timing Requirements        149   113 3.11        Power Sequence Timing Requirements        157
108 3.12        Digital I/O Specifications        153   114 3.12        Digital I/O Specifications        161
109 4        Management and Pre-OS Requirements        154   115 4        Management and Pre-OS Requirements        162
110 4.1        Sideband Management Interface and Transport        154   116 4.1        Sideband Management Interface and Transport        162
111 4.2        NC-SI Traffic        155   117 4.2        NC-SI Traffic        163
112 4.3        Management Controller (MC) MAC Address Provisioning        155   118 4.3        Management Controller (MC) MAC Address Provisioning        163
113 4.4        ASIC Die Temperature Reporting        157   119 4.4        ASIC Die Temperature Reporting        166
114 4.5        Power Consumption Reporting        160   120 4.5        Power Consumption Reporting        168
115 4.6        Pluggable Transceiver Module Status and Temperature Reporting        161   121 4.6        Pluggable Transceiver Module Status and Temperature Reporting        169
116 4.7        Management and Pre-OS Firmware Inventory and Update        161   122 4.7        Management and Pre-OS Firmware Inventory and Update        169
117 4.7.1        Secure Firmware        161   123 4.7.1        Secure Firmware        170
118 4.7.2        Firmware Inventory        162   124 4.7.2        Firmware Inventory        170
119 4.7.3        Firmware Inventory and Update in Multi-Host Environments        162   125 4.7.3        Firmware Inventory and Update in Multi-Host Environments        170
120 4.8        NC-SI Package Addressing and Hardware Arbitration Requirements        163   126 4.8        NC-SI Package Addressing and Hardware Arbitration Requirements        171
121 4.8.1        NC-SI over RBT Package Addressing        163   127 4.8.1        NC-SI over RBT Package Addressing        171
122 4.8.2        Arbitration Ring Connections        163   128 4.8.2        Arbitration Ring Connections        171
123 4.9        SMBus 2.0 Addressing Requirements        163   129 4.9        SMBus 2.0 Addressing Requirements        171
124 4.9.1        SMBus Address Map        164   130 4.9.1        SMBus Address Map        172
125 4.10        FRU EEPROM        164   131 4.10        FRU EEPROM        172
126 4.10.1        FRU EEPROM Addressing and Size        164   132 4.10.1        FRU EEPROM Addressing and Size        172
127 4.10.2        FRU EEPROM Write Protection        166   133 4.10.2        FRU EEPROM Write Protection        174
128 4.10.3        FRU EEPROM Content Requirements        166   134 4.10.3        FRU EEPROM Content Requirements        174
129 4.10.4        FRU Template        173   135 4.10.4        FRU Template        181
130 5        Routing Guidelines and Signal Integrity Considerations        174   136 5        Routing Guidelines and Signal Integrity Considerations        182
131 5.1        NC-SI over RBT        174   137 5.1        NC-SI over RBT        182
132 5.1.1        SFF Baseboard Requirements        175   138 5.1.1        SFF/TSFF Baseboard Requirements        183
133 5.1.2        LFF Baseboard Requirements        176   139 5.1.2        LFF Baseboard Requirements        184
134 5.1.3        SFF OCP NIC 3.0 Card Requirements        176   140 5.1.3        SFF/TSFF OCP NIC 3.0 Card Requirements        184
135 5.1.4        LFF OCP NIC 3.0 Card Requirements        177   141 5.1.4        LFF OCP NIC 3.0 Card Requirements        185
136 5.2        SMBus 2.0        177   142 5.2        SMBus 2.0        186
137 5.3        PCIe        178   143 5.3        PCIe        186
138 5.3.1        Channel Requirements        178   144 5.3.1        Channel Requirements        186
139 5.3.1.1        REFCLK requirements        178   145 5.3.1.1        REFCLK requirements        186
140 5.3.1.2        Add-in Card Electrical Budgets        178   146 5.3.1.2        Add-in Card Electrical Budgets        186
141 5.3.1.3        Baseboard Channel Budget        179   147 5.3.1.3        Baseboard Channel Budget        187
142 5.3.1.4        SFF-TA-1002 Connector Channel Budget        179   148 5.3.1.4        SFF-TA-1002 Connector Channel Budget        187
143 5.3.1.5        Differential Impedance (Informative)        179   149 5.3.1.5        Differential Impedance (Informative)        187
144 5.3.2        Test Fixtures        179   150 5.3.2        Test Fixtures        187
145 5.3.2.1        Compliance Load Board (CLB)        180   151 5.3.2.1        Compliance Load Board (CLB)        188
146 5.3.2.2        Compliance Baseboard (CBB)        181   152 5.3.2.2        Compliance Baseboard (CBB)        189
147 5.3.3        Test Methodology        181   153 5.3.3        Test Methodology        189
148 5.3.3.1        Test Setup        181   154 5.3.3.1        Test Setup        189
149 6        Thermal and Environmental        183   155 6        Thermal and Environmental        191
150 6.1        Airflow Direction        183   156 6.1        Airflow Direction        191
151 6.1.1        Hot Aisle Cooling        183   157 6.1.1        Hot Aisle Cooling        191
152 6.1.2        Cold Aisle Cooling        184   158 6.1.2        Cold Aisle Cooling        192
153 6.2        Thermal Design Guidelines        185   159 6.2        Thermal Design Guidelines        193
154 6.2.1        SFF Card ASIC Cooling – Hot Aisle        185   160 6.2.1        SFF Card ASIC Cooling – Hot Aisle        193
      161 6.2.2        TSFF Card ASIC Cooling – Hot Aisle (TBD)        197
155 6.2.2        LFF Card ASIC Cooling – Hot Aisle        189   162 6.2.3        LFF Card ASIC Cooling – Hot Aisle        197
156 6.2.3        SFF Card ASIC Cooling – Cold Aisle        191   163 6.2.4        SFF Card ASIC Cooling – Cold Aisle        199
      164 6.2.5        TSFF Card ASIC Cooling – Cold Aisle (TBD)        202
157 6.2.4        LFF Card ASIC Cooling – Cold Aisle        194   165 6.2.6        LFF Card ASIC Cooling – Cold Aisle        202
158 6.3        Thermal Simulation (CFD) Modeling        196   166 6.3        Thermal Simulation (CFD) Modeling        204
159 6.4        Thermal Test Fixture        196   167 6.4        Thermal Test Fixture        204
160 6.4.1        Test Fixture for SFF Card        197   168 6.4.1        Test Fixture for SFF Card        205
      169 6.4.2        Test Fixture for TSFF Card (TBD)        207
161 6.4.2        Test Fixture for LFF Card        199   170 6.4.3        Test Fixture for LFF Card        207
162 6.4.3        Test Fixture Airflow Direction        201   171 6.4.4        Test Fixture Airflow Direction        209
163 6.4.4        Thermal Test Fixture Candlestick Sensors        201   172 6.4.5        Thermal Test Fixture Candlestick Sensors        209
164 6.5        Card Sensor Requirements        204   173 6.5        Card Sensor Requirements        212
165 6.6        Card Cooling Tiers        204   174 6.6        Card Cooling Tiers        212
166 6.7        Non-Operational Shock & Vibration Testing        206   175 6.7        Non-Operational Shock & Vibration Testing        214
167 6.7.1        Shock & Vibe Test Fixture        206   176 6.7.1        Shock & Vibe Test Fixture        214
168 6.7.2        Test Procedure        207   177 6.7.2        Test Procedure        215
169 6.8        Dye and Pull Test Method        209   178 6.8        Dye and Pull Test Method        217
170 6.9        Gold Finger Plating Requirements        211   179 6.9        Gold Finger Plating Requirements        219
171 6.9.1        Host Side Gold Finger Plating Requirements        211   180 6.9.1        Host Side Gold Finger Plating Requirements        219
172 6.9.2        Line Side Gold Finger Durability Requirements        211   181 6.9.2        Line Side Gold Finger Durability Requirements        219
173 7        Regulatory        212   182 7        Regulatory        220
174 7.1        Required Compliance        212   183 7.1        Required Compliance        220
175 7.1.1        Required Environmental Compliance        212   184 7.1.1        Required Environmental Compliance        220
176 7.1.2        Required EMC Compliance        212   185 7.1.2        Required EMC Compliance        220
177 7.1.3        Required Product Safety Compliance        213   186 7.1.3        Required Product Safety Compliance        221
178 7.1.4        Required Immunity (ESD) Compliance        213   187 7.1.4        Required Immunity (ESD) Compliance        221
179 7.2        Recommended Compliance        214   188 7.2        Recommended Compliance        221
180 7.2.1        Recommended Environmental Compliance        214   189 7.2.1        Recommended Environmental Compliance        222
181 7.2.2        Recommended EMC Compliance        214   190 7.2.2        Recommended EMC Compliance        222
182 8        Revision History        215   191 8        Revision History        223
183 8.1        Document Revision History        215   192 8.1        Document Revision History        223
184 8.2        FRU Content Revision History        223   193 8.2        FRU Content Revision History        232
 
186 Figure 1: Representative SFF OCP NIC 3.0 Card with Dual QSFP Ports        16 <> 195 Figure 1: Representative SFF OCP NIC 3.0 Card with Dual QSFP Ports        19
187 Figure 2: Representative LFF OCP NIC 3.0 Card with Dual QSFP Ports and on-board DRAM        17   196 Figure 2: Representative LFF OCP NIC 3.0 Card with Dual QSFP Ports and on-board DRAM        19
188 Figure 3: SFF and LFF Block Diagrams (not to scale)        18   197 Figure 3: SFF/TSFF and LFF Block Diagrams (not to scale)        21
189 Figure 4: Primary Connector (4C+) and Secondary Connector (4C) (LFF) OCP NIC 3.0 Cards        22   198 Figure 4: Primary Connector (4C+) and Secondary Connector (4C) (LFF) OCP NIC 3.0 Cards        25
190 Figure 5: Primary Connector (4C+) Only (LFF) OCP NIC 3.0 Cards        23   199 Figure 5: Primary Connector (4C+) Only (LFF) OCP NIC 3.0 Cards        26
191 Figure 6: Primary Connector (4C+) with 4C and 2C (SFF) OCP NIC 3.0 Cards        23   200 Figure 6: Primary Connector (4C+) with 4C and 2C (SFF) OCP NIC 3.0 Cards        26
192 Figure 7: SFF NIC Configuration Views        25   201 Figure 7: SFF NIC Configuration Views        28
193 Figure 8: SFF NIC Line Side 3D Views        26   202 Figure 8: SFF NIC Line Side 3D Views        29
194 Figure 9: SFF NIC Chassis Mounted 3D Views        27   203 Figure 9: SFF NIC Chassis Mounted 3D Views        30
195 Figure 10: LFF NIC Configuration Views        29   204 Figure 10: LFF NIC Configuration Views        32
196 Figure 11: LFF NIC Line Side 3D Views        30   205 Figure 11: LFF NIC Line Side 3D Views        33
197 Figure 12: LFF NIC Chassis Mounted 3D Views        31   206 Figure 12: LFF NIC Chassis Mounted 3D Views        34
198 Figure 13: PBA Exploded Views (SFF and LFF)        33   207 Figure 13: PBA Exploded Views (SFF and LFF)        36
199 Figure 14: Faceplate Assembly Exploded Views (SFF and LFF)        34   208 Figure 14: Faceplate Assembly Exploded Views (SFF, TSFF and LFF)        38
200 Figure 15: SFF Generic I/O Faceplate with Pulltab Version (2D View)        37   209 Figure 15: SFF Generic I/O Faceplate – Pull Tab Version (2D View)        41
201 Figure 16: SFF Generic I/O Faceplate – Ejector Version (2D View)        37   210 Figure 16: SFF Generic I/O Faceplate – Ejector Version (2D View)        41
202 Figure 17: SFF Generic I/O Faceplate – Internal Lock Version (2D View)        38   211 Figure 17: SFF Generic I/O Faceplate – Internal Lock Version (2D View)        42
      212 Figure 18: TSFF Generic I/O Faceplate – Pull Tab Version (2D View)        42
      213 Figure 19: TSFF Generic I/O Faceplate – Ejector Version (2D View)        43
      214 Figure 20: TSFF Generic I/O Faceplate – Internal Lock Version (2D View)        43
203 Figure 18: LFF Generic I/O Faceplate – Ejector Version (2D View)        38   215 Figure 21: LFF Generic I/O Faceplate – Ejector Version (2D View)        44
204 Figure 19: SFF I/O Faceplate – Ejector Lever (2D View)        39   216 Figure 22: SFF I/O Faceplate – Ejector Lever (2D View)        45
205 Figure 20: LFF I/O Faceplate – Ejector Lever (2D View)        40   217 Figure 23: LFF I/O Faceplate – Ejector Lever (2D View)        46
206 Figure 21: Ejector Lock        41   218 Figure 24: Ejector Lock        47
207 Figure 22: Clinch Nut Option A        42   219 Figure 25: Clinch Nut Option A        48
208 Figure 23: Clinch Nut Option B        42   220 Figure 26: Clinch Nut Option B        48
209 Figure 24: SFF Keep Out Zone – Top View        43   221 Figure 27: SFF Keep Out Zone – Top View        49
210 Figure 25: SFF Keep Out Zone – Top View – Detail A        44   222 Figure 28: SFF Keep Out Zone – Top View – Detail A        50
211 Figure 26: SFF Keep Out Zone – Bottom View        44   223 Figure 29: SFF Keep Out Zone – Bottom View        50
212 Figure 27: SFF Keep Out Zone – Side View        45   224 Figure 30: SFF Keep Out Zone – Side View        51
213 Figure 28: SFF Keep Out Zone – Side View – Detail D        45   225 Figure 31: SFF Keep Out Zone – Side View – Detail D        51
      226 Figure 32: TSFF Keep Out Zone – Side View        52
214 Figure 29: LFF Keep Out Zone – Top View        46   227 Figure 33: LFF Keep Out Zone – Top View        53
215 Figure 30: LFF Keep Out Zone – Top View – Detail A        47   228 Figure 34: LFF Keep Out Zone – Top View – Detail A        54
216 Figure 31: LFF Keep Out Zone – Bottom View        48   229 Figure 35: LFF Keep Out Zone – Bottom View        55
217 Figure 32: LFF Keep Out Zone – Side View        48   230 Figure 36: LFF Keep Out Zone – Side View        55
218 Figure 33: LFF Keep Out Zone – Side View – Detail D        49   231 Figure 37: LFF Keep Out Zone – Side View – Detail D        56
219 Figure 34: SFF Bottom Side Insulator (3D View)        50   232 Figure 38: SFF, TSFF Bottom Side Insulator (3D View)        57
220 Figure 35: SFF Bottom Side Insulator (Top and Side View)        51   233 Figure 39: SFF, TSFF Bottom Side Insulator (Top and Side View)        58
221 Figure 36: SFF Bottom Side Insulator (alternate) (Top and Side View)        52   234 Figure 40: SFF, TSFF Bottom Side Insulator (alternate) (Top and Side View)        59
222 Figure 37: LFF Bottom Side Insulator (3D View)        52   235 Figure 41: LFF Bottom Side Insulator (3D View)        59
223 Figure 38: LFF Bottom Side Insulator (Top and Side View)        53   236 Figure 42: LFF Bottom Side Insulator (Top and Side View)        60
224 Figure 39: LFF Bottom Side Insulator (alternate) (Top and Side View)        54   237 Figure 43: LFF Bottom Side Insulator (alternate) (Top and Side View)        61
225 Figure 40: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View)        55   238 Figure 44: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View)        62
226 Figure 41: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View)        56   239 Figure 45: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View)        63
227 Figure 42: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View)        56   240 Figure 46: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View)        63
228 Figure 43: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View)        57   241 Figure 47: SFF OCP NIC 3.0 Card with Ejector Latch CTF Dimensions (Top View)        64
229 Figure 44: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)        57   242 Figure 48: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)        64
230 Figure 45: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)        58   243 Figure 49: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)        65
231 Figure 46: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View)        58   244 Figure 50: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View)        65
232 Figure 47: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Front View)        59   245 Figure 51: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Front View)        66
233 Figure 48: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Side View)        59   246 Figure 52: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Side View)        66
234 Figure 49: SFF Baseboard Chassis CTF Dimensions (Rear View)        59   247 Figure 53: SFF Baseboard Chassis CTF Dimensions (Rear View)        66
235 Figure 50: SFF Baseboard Chassis to Card Thumb Screw CTF Dimensions (Side View)        60   248 Figure 54: SFF Baseboard Chassis to Card Thumb Screw CTF Dimensions (Side View)        67
236 Figure 51: SFF Baseboard Chassis to Ejector lever Card CTF Dimensions (Side View)        60   249 Figure 55: SFF Baseboard Chassis to Ejector lever Card CTF Dimensions (Side View)        67
237 Figure 52: SFF Baseboard Chassis CTF Dimensions (Rear Rail Guide View)        60   250 Figure 56: SFF Baseboard Chassis CTF Dimensions (Rear Rail Guide View)        67
238 Figure 53: SFF Baseboard Chassis CTF Dimensions (Rail Guide Detail) – Detail C        61   251 Figure 57: SFF Baseboard Chassis CTF Dimensions (Rail Guide Detail) – Detail C        68
      252 Figure 58: TSFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View)        69
239 Figure 54: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View)        62   253 Figure 59: TSFF OCP NIC 3.0 Card with Ejector Latch CTF Dimensions (Top View)        69
      254 Figure 60: TSFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View)        69
      255 Figure 61: TSFF Baseboard Chassis CTF Dimensions (Rear View)        69
      256 Figure 62: LFF OCP NIC 3.0 Card with Ejector Latch CTF Dimensions (Top View)        70
240 Figure 55: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)        62   257 Figure 63: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)        70
241 Figure 56: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)        63   258 Figure 64: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)        71
242 Figure 57: LFF Baseboard Chassis CTF Dimensions (Rear View)        63   259 Figure 65: LFF Baseboard Chassis CTF Dimensions (Rear View)        71
243 Figure 58: LFF Baseboard Chassis CTF Dimensions (Side View)        64   260 Figure 66: LFF Baseboard Chassis CTF Dimensions (Side View)        72
244 Figure 59: LFF Baseboard Chassis CTF Dimensions (Rail Guide View)        64   261 Figure 67: LFF Baseboard Chassis CTF Dimensions (Rail Guide View)        72
245 Figure 60: LFF Baseboard Chassis CTF Dimensions (Rail Guide – Detail C)        64   262 Figure 68: LFF Baseboard Chassis CTF Dimensions (Rail Guide – Detail C)        72
246 Figure 61: SFF Label Area Example        66   263 Figure 69: SFF, TSFF Label Area Example        74
247 Figure 62: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        68   264 Figure 70: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        76
248 Figure 63: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller        69   265 Figure 71: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller        77
249 Figure 64: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers        69   266 Figure 72: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers        77
250 Figure 65: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller        70   267 Figure 73: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller        78
251 Figure 66: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller        70   268 Figure 74: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller        78
252 Figure 67: SFF Primary Connector Gold Finger Dimensions – x16 – Top Side (“B” Pins)        72   269 Figure 75: SFF, TSFF Primary Connector Gold Finger Dimensions – x16 – Top Side (“B” Pins)        80
253 Figure 68: SFF Primary Connector Card Profile Dimensions        73   270 Figure 76: SFF, TSFF Primary Connector Card Profile Dimensions        81
254 Figure 69: SFF Primary Conector Gold Finger - Detail D        73   271 Figure 77: SFF, TSFF Primary Conector Gold Finger - Detail D        81
255 Figure 70: LFF Gold Finger Dimensions – x32 – Top Side (“B” Pins)        74   272 Figure 78: LFF Gold Finger Dimensions – x32 – Top Side (“B” Pins)        82
256 Figure 71: LFF Gold Finger Dimensions – x32 – Bottom Side (“A” Pins)        74   273 Figure 79: LFF Gold Finger Dimensions – x32 – Bottom Side (“A” Pins)        82
257 Figure 72: 168-pin Base Board Primary Connector – Right Angle        78   274 Figure 80: 168-pin Base Board Primary Connector – Right Angle        86
258 Figure 73: 140-pin Base Board Secondary Connector – Right Angle        79   275 Figure 81: 140-pin Base Board Secondary Connector – Right Angle        87
259 Figure 74: OCP NIC 3.0 Card and Host Offset for Right Angle Connectors        79   276 Figure 82: OCP NIC 3.0 Card and Host Offset for Right Angle Connectors        87
260 Figure 75: 168-pin Base Board Primary Connector – Straddle Mount        80   277 Figure 83: 168-pin Base Board Primary Connector – Straddle Mount        88
261 Figure 76: 140-pin Base Board Secondary Connector – Straddle Mount        80   278 Figure 84: 140-pin Base Board Secondary Connector – Straddle Mount        88
262 Figure 77: OCP NIC 3.0 Card and Baseboard PCB Thickness Options for Straddle Mount Connectors        81   279 Figure 85: OCP NIC 3.0 Card and Baseboard PCB Thickness Options for Straddle Mount Connectors        89
263 Figure 78: 0 mm Offset (Coplanar) for 0.062” Thick Baseboards        81   280 Figure 86: 0 mm Offset (Coplanar) for 0.062” Thick Baseboards        89
264 Figure 79: 0.3 mm Offset for 0.076” Thick Baseboards        82   281 Figure 87: 0.3 mm Offset for 0.076” Thick Baseboards        90
265 Figure 80: Primary and Secondary Connector Locations for LFF Support with Right Angle Connectors        82   282 Figure 88: Primary and Secondary Connector Locations for LFF Support with Right Angle Connectors        90
266 Figure 81: Primary and Secondary Connector Locations for LFF Support with Straddle Mount Connectors        82   283 Figure 89: Primary and Secondary Connector Locations for LFF Support with Straddle Mount Connectors        90
267 Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[2:0]#)        94   284 Figure 90: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[2:0]#)        103
268 Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[2:0]#)        94   285 Figure 91: PCIe Present and Bifurcation Control Pins (Static BIF[2:0]#)        103
269 Figure 84: Example SMBus Connections        96   286 Figure 92: Example SMBus Connections        105
270 Figure 85: NC-SI over RBT Connection Example – Single Primary Connector        102   287 Figure 93: NC-SI over RBT Connection Example – Single Primary Connector        111
271 Figure 86: NC-SI over RBT Connection Example – Dual Primary Connectors        103   288 Figure 94: NC-SI over RBT Connection Example – Dual Primary Connectors        112
272 Figure 87: Scan Chain Timing Diagram Example 1        106   289 Figure 95: Scan Chain Timing Diagram Example 1        115
273 Figure 88: Scan Chain Timing Diagram Example 2        106   290 Figure 96: Scan Chain Timing Diagram Example 2        115
274 Figure 89: Scan Chain Connection Example        112   291 Figure 97: Scan Chain Connection Example        121
275 Figure 90: Example Power Supply Topology        117   292 Figure 98: Example Power Supply Topology        126
276 Figure 91: USB 2.0 Connection Example – Basic Connectivity        119   293 Figure 99: USB 2.0 Connection Example – Basic Connectivity        128
277 Figure 92: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity        119   294 Figure 100: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity        128
278 Figure 93: UART Connection Example        121   295 Figure 101: UART Connection Example        130
279 Figure 94: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller)        127   296 Figure 102: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller)        135
280 Figure 95: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)        128   297 Figure 103: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)        136
281 Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller)        129   298 Figure 104: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller)        137
282 Figure 97: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers)        130   299 Figure 105: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers)        138
283 Figure 98: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)        131   300 Figure 106: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)        139
284 Figure 99: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links        133   301 Figure 107: SFF/TSFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links        141
285 Figure 100: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links        134   302 Figure 108: SFF/TSFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links        142
286 Figure 101: SFF PCIe REFCLK Mapping – Quad Host – 4 Links        135   303 Figure 109: SFF/TSFF PCIe REFCLK Mapping – Quad Host – 4 Links        143
287 Figure 102: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links        136   304 Figure 110: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links        144
288 Figure 103: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links        137   305 Figure 111: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links        145
289 Figure 104: LFF PCIe REFCLK Mapping – Quad Host – 4 Links        138   306 Figure 112: LFF PCIe REFCLK Mapping – Quad Host – 4 Links        146
290 Figure 105: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement        142   307 Figure 113: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement        150
291 Figure 106: Baseboard Power States        144   308 Figure 114: Baseboard Power States        152
292 Figure 107: Power-Up Sequencing – Normal Operation        149   309 Figure 115: Power-Up Sequencing – Normal Operation        157
293 Figure 108: Power-Down Sequencing – Normal Operation        150   310 Figure 116: Power-Down Sequencing – Normal Operation        158
294 Figure 109: Programming Mode Sequencing        151   311 Figure 117: Programming Mode Sequencing        159
295 Figure 110: FRU EEPROM Writes with Double Byte Addressing        165   312 Figure 118: FRU EEPROM Writes with Double Byte Addressing        173
296 Figure 111: FRU EEPROM Reads with Double Byte Addressing        165   313 Figure 119: FRU EEPROM Reads with Double Byte Addressing        173
297 Figure 112: FRU Update Flow        166   314 Figure 120: FRU Update Flow        174
298 Figure 113: NC-SI over RBT Timing Budget Topology        175   315 Figure 121: NC-SI over RBT Timing Budget Topology        183
299 Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer        177   316 Figure 122: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer        185
300 Figure 115: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer        177   317 Figure 123: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer        185
301 Figure 116: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF        180   318 Figure 124: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF/TSFF        188
302 Figure 117: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF        181   319 Figure 125: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF/TSFF        189
303 Figure 118: Airflow Direction for Hot Aisle Cooling (SFF and LFF)        183   320 Figure 126: Airflow Direction for Hot Aisle Cooling (SFF/TSFF and LFF)        191
304 Figure 119: Airflow Direction for Cold Aisle Cooling (SFF and LFF)        184   321 Figure 127: Airflow Direction for Cold Aisle Cooling (SFF/TSFF and LFF)        192
305 Figure 120: ASIC Supportable Power for Hot Aisle Cooling – SFF        185   322 Figure 128: ASIC Supportable Power for Hot Aisle Cooling – SFF        193
306 Figure 121: OCP NIC 3.0 SFF Reference Design and CFD Geometry        186   323 Figure 129: OCP NIC 3.0 SFF Reference Design and CFD Geometry        194
307 Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling        187   324 Figure 130: Server System Airflow Capability – SFF Card Hot Aisle Cooling        195
308 Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in Aux Power Mode        188   325 Figure 131: Server System Airflow Capability – SFF Card Hot Aisle Cooling in Aux Power Mode        196
309 Figure 124: ASIC Supportable Power for Hot Aisle Cooling – LFF Card        189   326 Figure 132: ASIC Supportable Power for Hot Aisle Cooling – LFF Card        197
310 Figure 125: OCP NIC 3.0 LFF Reference Design and CFD Geometry        189   327 Figure 133: OCP NIC 3.0 LFF Reference Design and CFD Geometry        197
311 Figure 126: Server System Airflow Capability – LFF Card Hot Aisle Cooling        191   328 Figure 134: Server System Airflow Capability – LFF Card Hot Aisle Cooling        199
312 Figure 127: ASIC Supportable Power for Cold Aisle Cooling – SFF Card        192   329 Figure 135: ASIC Supportable Power for Cold Aisle Cooling – SFF Card        200
313 Figure 128: Server System Airflow Capability – SFF Cold Aisle Cooling        193   330 Figure 136: Server System Airflow Capability – SFF Cold Aisle Cooling        201
314 Figure 129: ASIC Supportable Power Comparison – SFF Card        193   331 Figure 137: ASIC Supportable Power Comparison – SFF Card        201
315 Figure 130: ASIC Supportable Power for Cold Aisle Cooling – LFF Card        194   332 Figure 138: ASIC Supportable Power for Cold Aisle Cooling – LFF Card        202
316 Figure 131: Server System Airflow Capability – LFF Cold Aisle Cooling        195   333 Figure 139: Server System Airflow Capability – LFF Cold Aisle Cooling        203
317 Figure 132: ASIC Supportable Power Comparison – LFF Card        195   334 Figure 140: ASIC Supportable Power Comparison – LFF Card        203
318 Figure 133: SFF Thermal Test Fixture Preliminary Design        197   335 Figure 141: SFF Thermal Test Fixture Preliminary Design        205
319 Figure 134: SFF Thermal Test Fixture Preliminary Design – Cover Removed        198   336 Figure 142: SFF Thermal Test Fixture Preliminary Design – Cover Removed        206
320 Figure 135: SFF Card Thermal Test Fixture PCB        198   337 Figure 143: SFF Card Thermal Test Fixture PCB        206
321 Figure 136: LFF Card Thermal Test Fixture Design        199   338 Figure 144: LFF Card Thermal Test Fixture Design        207
322 Figure 137: LFF Card Thermal Test Fixture Design – Cover Removed        199   339 Figure 145: LFF Card Thermal Test Fixture Design – Cover Removed        207
323 Figure 138: LFF Card Thermal Test Fixture PCB        200   340 Figure 146: LFF Card Thermal Test Fixture PCB        208
324 Figure 139: Thermal Test Fixture Airflow Direction        201   341 Figure 147: Thermal Test Fixture Airflow Direction        209
325 Figure 140: External Thermocouple Placement for Cold Aisle Inlet Temperature Measurement        202   342 Figure 148: External Thermocouple Placement for Cold Aisle Inlet Temperature Measurement        210
326 Figure 140: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow        203   343 Figure 149: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow        211
      344 Figure 150: TSFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow (TBD)        211
327 Figure 141: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow        203   345 Figure 151: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow        211
328 Figure 142: Graphical View of Card Cooling Tiers        205   346 Figure 152: Graphical View of Card Cooling Tiers        213
329 Figure 143: Typical Operating Range for Hot Aisle Configurations        205   347 Figure 153: Typical Operating Range for Hot Aisle Configurations        213
330 Figure 144: Typical Operating Range for Cold Aisle Configurations        206   348 Figure 154: Typical Operating Range for Cold Aisle Configurations        214
331 Figure 145: SFF Shock and Vibe Fixture        207   349 Figure 155: SFF/TSFF Shock and Vibe Fixture        215
332 Figure 146: LFF Shock and Vibe Fixture        207   350 Figure 156: LFF Shock and Vibe Fixture        215
333 Figure 147: Dye and Pull Type Locations        210   351 Figure 157: Dye and Pull Type Locations        218
334 Figure 148: Dye Coverage Percentage        210   352 Figure 158: Dye Coverage Percentage        218
 
336 Table 1: Acknowledgements – Current Contributors – By Company        11 <> 354 Table 1: Acknowledgements – Current Contributors – By Company        12
337 Table 2: Acronyms        14   355 Table 2: Acronyms        15
338 Table 3: OCP 3.0 Form Factor Dimensions        19   356 Table 3: OCP NIC 3.0 Form Factor Dimensions        22
339 Table 4: Baseboard to OCP NIC Form Factor Compatibility Chart        19   357 Table 4: Baseboard to OCP NIC Form Factor Compatibility Chart        22
340 Table 5: Example Non-NIC Use Cases        21   358 Table 5: Example Non-NIC Use Cases        24
341 Table 6: OCP NIC 3.0 Card Definitions        24   359 Table 6: OCP NIC 3.0 Card Definitions        27
342 Table 7: OCP NIC 3.0 Line Side I/O Implementations        32   360 Table 7: OCP NIC 3.0 Line Side I/O Implementations        35
343 Table 8: Line Side I/O Cross Reference to Industry Standards        32   361 Table 8: Line Side I/O Cross Reference to Industry Standards        35
344 Table 9: Bill of Materials for the SFF and LFF Faceplate Assemblies        35   362 Table 9: Bill of Materials for the SFF and LFF Faceplate Assemblies        39
345 Table 10: CTF Default Tolerances (SFF and LFF OCP NIC 3.0)        55   363 Table 10: CTF Default Tolerances (SFF, TSFF and LFF OCP NIC 3.0)        62
346 Table 11: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        68   364 Table 11: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        76
347 Table 12: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller        68   365 Table 12: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller        76
348 Table 13: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controller        69   366 Table 13: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controller        77
349 Table 14: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller        70   367 Table 14: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller        78
350 Table 15: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller        70   368 Table 15: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller        78
351 Table 16: NIC Implementation Examples and 3D CAD        71   369 Table 16: NIC Implementation Examples and 3D CAD        79
352 Table 17: Contact Mating Positions for the Primary Connector        74   370 Table 17: Contact Mating Positions for the Primary Connector        82
353 Table 18: Contact Mating Positions for the Secondary Connector        76   371 Table 18: Contact Mating Positions for the Secondary Connector        84
354 Table 19: Right Angle Connector Options        78   372 Table 19: Right Angle Connector Options        86
355 Table 20: Straddle Mount Connector Options        79   373 Table 20: Straddle Mount Connector Options        87
356 Table 21: Primary Connector Pin Definition (x16) (4C+)        83   374 Table 21: Primary Connector Pin Definition (x16) (4C+)        91
357 Table 22: Secondary Connector Pin Definition (x16) (4C)        85   375 Table 22: Secondary Connector Pin Definition (x16) (4C)        93
358 Table 23: Pin Descriptions – PCIe        87   376 Table 23: Pin Descriptions – PCIe        95
359 Table 24: Pin Descriptions – PCIe Present and Bifurcation Control Pins        92   377 Table 24: Pin Descriptions – PCIe Present and Bifurcation Control Pins        101
360 Table 25: Pin Descriptions – SMBus        95   378 Table 25: Pin Descriptions – SMBus        104
361 Table 26: Pin Descriptions – NC-SI over RBT        96   379 Table 26: Pin Descriptions – NC-SI over RBT        106
362 Table 27: Pin Descriptions – Scan Chain        104   380 Table 27: Pin Descriptions – Scan Chain        113
363 Table 28: Scan Chain Timing Requirements – Baseboard Side        106   381 Table 28: Scan Chain Timing Requirements – Baseboard Side        115
364 Table 29: Scan Chain Timing Requirements – OCP NIC 3.0 Card Side        106   382 Table 29: Scan Chain Timing Requirements – OCP NIC 3.0 Card Side        115
365 Table 30: Pin Descriptions – Scan Chain DATA_OUT Bit Definition        107   383 Table 30: Pin Descriptions – Scan Chain DATA_OUT Bit Definition        116
366 Table 31: Pin Descriptions – Scan Chain DATA_IN Bit Definition        107   384 Table 31: Pin Descriptions – Scan Chain DATA_IN Bit Definition        116
367 Table 32: Pin Descriptions – Power        113   385 Table 32: Pin Descriptions – Power        122
368 Table 33: Pin Descriptions – USB 2.0 – Primary Connector only        118   386 Table 33: Pin Descriptions – USB 2.0 – Primary Connector only        127
369 Table 34: Pin Descriptions – UART – Secondary Connector Only        120   387 Table 34: Pin Descriptions – UART – Secondary Connector Only        129
370 Table 35: Pin Descriptions – RFU[1:4]        122   388 Table 35: Pin Descriptions – RFU[1:4]        130
371 Table 36: PCIe Bifurcation Decoder for x32, x16, x8, x4, x2 and x1 Card Widths        125   389 Table 36: PCIe Bifurcation Decoder for x32, x16, x8, x4, x2 and x1 Card Widths        133
372 Table 37: PCIe REFCLK and PERST Associations        132   390 Table 37: PCIe REFCLK and PERST Associations        140
373 Table 38: SFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links        132   391 Table 38: SFF, TSFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links        140
374 Table 39: LFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2, 4 and 8 Links        132   392 Table 39: LFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2, 4 and 8 Links        140
375 Table 40: OCP NIC 3.0 Card LED Configuration with Two Physical LEDs per Port        140   393 Table 40: OCP NIC 3.0 Card LED Configuration with Two Physical LEDs per Port        148
376 Table 41: Available Card Functions per Power State        145   394 Table 41: Available Card Functions per Power State        153
377 Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes        147   395 Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes        155
378 Table 43: Power Sequencing Parameters        151   396 Table 43: Power Sequencing Parameters        159
379 Table 44: Digital I/O DC specifications        153   397 Table 44: Digital I/O DC specifications        161
380 Table 45: Digital I/O AC specifications        153   398 Table 45: Digital I/O AC specifications        161
381 Table 46: OCP NIC 3.0 Management Implementation Definitions        154   399 Table 46: OCP NIC 3.0 Management Implementation Definitions        162
382 Table 47: Sideband Management Interface and Transport Requirements        154   400 Table 47: Sideband Management Interface and Transport Requirements        162
383 Table 48: NC-SI Traffic Requirements        155   401 Table 48: NC-SI Traffic Requirements        163
384 Table 49: MC MAC Address Provisioning Requirements        155   402 Table 49: MC MAC Address Provisioning Requirements        163
385 Table 50: Threshold Severity Level vs Example Threshold Values        158   403 Table 50: Threshold Severity Level vs Example Threshold Values        166
386 Table 51: Temperature Reporting Requirements        158   404 Table 51: Temperature Reporting Requirements        167
387 Table 52: Power Consumption Reporting Requirements        160   405 Table 52: Power Consumption Reporting Requirements        168
388 Table 53: Pluggable Module Status Reporting Requirements        161   406 Table 53: Pluggable Module Status Reporting Requirements        169
389 Table 54: Management and Pre-OS Firmware Inventory and Update Requirements        161   407 Table 54: Management and Pre-OS Firmware Inventory and Update Requirements        169
390 Table 55: Slot_ID[1:0] to Package ID[2:0] Mapping        163   408 Table 55: Slot_ID[1:0] to Package ID[2:0] Mapping        171
391 Table 56: FRU EEPROM Address Map        164   409 Table 56: FRU EEPROM Address Map        172
392 Table 57: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00        167   410 Table 57: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00        175
393 Table 58: NC-SI over RBT Timing Parameters        174   411 Table 58: NC-SI over RBT Timing Parameters        182
394 Table 59: PCIe Electrical Budgets        178   412 Table 59: PCIe Electrical Budgets        186
395 Table 60: PCIe Test Fixtures for OCP NIC 3.0        179   413 Table 60: PCIe Test Fixtures for OCP NIC 3.0        187
396 Table 61: Hot Aisle Air Temperature Boundary Conditions        184   414 Table 61: Hot Aisle Air Temperature Boundary Conditions        192
397 Table 62: Hot Aisle Airflow Boundary Conditions        184   415 Table 62: Hot Aisle Airflow Boundary Conditions        192
398 Table 63: Cold Aisle Air Temperature Boundary Conditions        184   416 Table 63: Cold Aisle Air Temperature Boundary Conditions        192
399 Table 64: Cold Aisle Airflow Boundary Conditions        185   417 Table 64: Cold Aisle Airflow Boundary Conditions        193
400 Table 65: Reference OCP NIC 3.0 SFF Card Geometry        186   418 Table 65: Reference OCP NIC 3.0 SFF Card Geometry        194
401 Table 66: Reference OCP NIC 3.0 LFF Card Geometry        190   419 Table 66: Reference OCP NIC 3.0 LFF Card Geometry        198
402 Table 67: Card Cooling Tier Definitions (LFM)        204   420 Table 67: Card Cooling Tier Definitions (LFM)        212
403 Table 68: Random Vibration Testing 1.88 GRMS Profile        208   421 Table 68: Random Vibration Testing 1.88 GRMS Profile        216
404 Table 69: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location        212   422 Table 69: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location        220
405 Table 70: Safety Requirements        213   423 Table 70: Safety Requirements        221
406 Table 71: Immunity (ESD) Requirements        213   424 Table 71: Immunity (ESD) Requirements        221
 
413 Your use of this Specification may be subject to other third party rights. THIS SPECIFICATION IS PROVIDED "AS IS." The contributors expressly disclaim any warranties (express, implied, or otherwise), including implied warranties of merchantability, non-infringement, fitness for a particular purpose, or title, related to the Specification. The Specification implementer and user assume the entire risk as to implementing or otherwise using the Specification. IN NO EVENT WILL ANY PARTY BE LIABLE TO ANY OTHER PARTY FOR LOST PROFITS OR ANY FORM OF INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES OF ANY CHARACTER FROM ANY CAUSES OF ACTION OF ANY KIND WITH RESPECT TO THIS SPECIFICATION OR ITS GOVERNING AGREEMENT, WHETHER BASED ON BREACH OF CONTRACT, TORT (INCLUDING NEGLIGENCE), OR OTHERWISE, AND WHETHER OR NOT THE OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. <> 431 Your use of this Specification may be subject to other third-party rights. THIS SPECIFICATION IS PROVIDED "AS IS." The contributors expressly disclaim any warranties (express, implied, or otherwise), including implied warranties of merchantability, non-infringement, fitness for a particular purpose, or title, related to the Specification. The Specification implementer and user assume the entire risk as to implementing or otherwise using the Specification. IN NO EVENT WILL ANY PARTY BE LIABLE TO ANY OTHER PARTY FOR LOST PROFITS OR ANY FORM OF INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES OF ANY CHARACTER FROM ANY CAUSES OF ACTION OF ANY KIND WITH RESPECT TO THIS SPECIFICATION OR ITS GOVERNING AGREEMENT, WHETHER BASED ON BREACH OF CONTRACT, TORT (INCLUDING NEGLIGENCE), OR OTHERWISE, AND WHETHER OR NOT THE OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
415 The OCP NIC 3.0 specification was created under a collaboration from many OCP member companies, and facilitated by the OCP NIC Subgroup under the OCP Server Workgroup. <> 433 The OCP NIC 3.0 specification was created under a collaboration from many OCP member companies and facilitated by the OCP NIC Subgroup under the OCP Server Workgroup.
 
419 Lenovo Group Ltd <> 437 Marvell Semiconductor, Inc.
 
421 Marvell Semiconductor, Inc. <> 439 Molex LLC
 
425 NVIDIA <> 443 NVIDIA Corporation
 
    -+ 450 Lenovo Group Ltd
 
    -+ 576 OSFP-RHS
      577 Octal Small Form Factor Pluggable Riding Heat Sink
 
    -+ 592 QSFP-DD
      593 Quad Small Form Factor Pluggable Double Density
 
    -+ 624 TSFF
      625 Tall Small Form Factor
 
620 The OCP NIC 3.0 specification is a follow-on to the OCP Mezz 2.0 rev 1.00 design specification. The OCP NIC 3.0 specification supports two basic card sizes: Small Form Factor (SFF), and Large Form Factor (LFF). The SFF allows for up to 16 PCIe® lanes on the card edge while the LFF supports up to 32 PCIe lanes. Compared to the OCP Mezz Card 2.0 Design Specification, the updated OCP NIC 3.0 specification provides a broader solution space for the NIC and system vendors to support the following use case scenarios: <> 645 The OCP NIC 3.0 specification is a follow-on to the OCP Mezz 2.0 rev 1.00 design specification. The OCP NIC 3.0 specification supports three basic card sizes: Small Form Factor (SFF), Tall Small Form Factor (TSFF) and Large Form Factor (LFF). The SFF and TSFF allows for up to 16 PCIe® lanes on the card edge while the LFF supports up to 32 PCIe lanes. The SFF and TSFF share the same board footprint. The TSFF has a taller faceplate to accommodate a taller heatsink and board level components. Compared to the OCP Mezz Card 2.0 Design Specification, the updated OCP NIC 3.0 specification provides a broader solution space for the NIC and system vendors to support the following use case scenarios:
 
622 Power delivery supports up to 80 W to a single connector (SFF) card, and up to 150 W to a dual connector (LFF) card <> 647 Power delivery supports up to 80 W to a single connector (SFF, TSFF) card, and up to 150 W to a dual connector (LFF) card
 
631 A representative SFF OCP NIC 3.0 card is shown in Figure 1 and a representative LFF is shown in Figure 2. <> 656 A representative SFF OCP NIC 3.0 card is shown in Figure 1. A representative TSFF is shown in Figure 2 and a LFF is shown in Figure 3.
 
    <> 658 Figure 2: Representative TSFF OCP NIC 3.0 Card with Dual QSFP Ports
633 Figure 2: Representative LFF OCP NIC 3.0 Card with Dual QSFP Ports and on-board DRAM   659 Figure 3: Representative LFF OCP NIC 3.0 Card with Dual QSFP Ports and on-board DRAM
 
641 OCP NIC 3.0 cards have two form factors – SFF and LFF. These cards are shown in Figure 3 below. The components shown in the figures are for illustrative purposes. The SFF uses one connector (Primary Connector) on the baseboard. The LFF uses one or two connectors (Primary Connector only or both the Primary and Secondary Connectors) on the baseboard. <> 667 OCP NIC 3.0 cards have three form factors – SFF, TSFF and LFF. These cards are shown in Figure 4 below. The components shown in the figures are for illustrative purposes. The SFF and TSFF uses one connector (Primary Connector) on the baseboard. The LFF uses one or two connectors (Primary Connector only or both the Primary and Secondary Connectors) on the baseboard.
642 Both the Primary and Secondary Connectors and card edge gold fingers are defined in and compliant to SFF-TA-1002. The Primary Connector is the “4C+” variant, the Secondary Connector is the “4C” version. On the OCP NIC 3.0 card side, the card edge is implemented with gold fingers. The SFF gold finger area only occupies the Primary Connector area for up to 16 PCIe lanes. The LFF gold finger area may occupy both the Primary and Secondary Connectors for up to 32 PCIe lanes, or optionally just the Primary Connector for up to 16 PCIe lane implementations.   668 Both the Primary and Secondary Connectors and card edge gold fingers are defined in and compliant to SFF-TA-1002. The Primary Connector is the “4C+” variant, the Secondary Connector is the “4C” version. On the OCP NIC 3.0 card side, the card edge is implemented with gold fingers. The SFF and TSFF gold finger area only occupies the Primary Connector area for up to 16 PCIe lanes. The LFF gold finger area may occupy both the Primary and Secondary Connectors for up to 32 PCIe lanes, or optionally just the Primary Connector for up to 16 PCIe lane implementations.
643 Figure 3: SFF and LFF Block Diagrams (not to scale)   669 Figure 4: SFF/TSFF and LFF Block Diagrams (not to scale)
 
646 Table 3: OCP 3.0 Form Factor Dimensions <> 672 Table 3: OCP NIC 3.0 Form Factor Dimensions
 
    -+ 676 Max Z-height
 
654 W1 = 76 mm <> 681 76 mm (W1)
655 L = 115 mm   682 115 mm
      683 11.50 mm
 
    -+ 688 TSFF
      689 76 mm (W1)
      690 115 mm
      691 14.20 mm
      692 “4C+”
      693 168 pins
      694 N/A
      695 Higher thermal dissipation compared to SFF cards with the additional Z-height.
 
661 W2 = 139 mm <> 697 139 mm (W2)
662 L = 115 mm   698 115 mm
      699 11.50 mm
 
668 The OCP NIC 3.0 design allows downward compatibility between the two card sizes. Table 4 shows the compatibility between the baseboard and NIC combinations. A SFF baseboard slot may only accept a SFF sized NIC. A LFF baseboard slot may accept a SFF or LFF NIC. <> 705 The OCP NIC 3.0 design allows downward compatibility between the three card sizes. Table 4 shows the compatibility between the baseboard and NIC combinations. A SFF baseboard slot may only accept a SFF sized NIC. A LFF baseboard slot may mechanically accept a SFF or LFF NIC using a guide rail adapter, and a TSFF baseboard slot may mechanically accept a TSFF or SFF NIC, however, these combinations are outside the scope of the specification.
 
    -+ 714 TSFF
      715 Up to 16 PCIe lanes
      716 Not Supported
 
683 This specification defines the form factor at the OCP NIC 3.0 card level, including the front panel, latching mechanism and card guide features. <> 723 This specification defines the form factor at the OCP NIC 3.0 card level for the SFF, TSFF and LFF, including the front panel, latching mechanism and card guide features.
 
686 This specification defines the electrical interface between baseboard and the OCP NIC 3.0 card. The electrical interface is implemented with a right angle or straddle mount connector on baseboard and gold finger on the OCP NIC 3.0 card. As previously noted in the mechanical overview, each card may implement a Primary Connector or Primary + Secondary Connector. Cards using only the Primary Connector are suitable for both the SFF and LFF and may support up to 16 lanes of PCIe. The Secondary Connector, when used in conjunction with the Primary Connector, allows LFF implementations and may support up to 32 lanes of PCIe. <> 726 This specification defines the electrical interface between baseboard and the OCP NIC 3.0 card. The electrical interface is implemented with a right angle or straddle mount connector on baseboard and gold finger on the OCP NIC 3.0 card. As previously noted in the mechanical overview, each card may implement a Primary Connector or Primary + Secondary Connector. Cards using only the Primary Connector are suitable for SFF, TSFF and LFF and may support up to 16 lanes of PCIe. The Secondary Connector, when used in conjunction with the Primary Connector, allows LFF implementations and may support up to 32 lanes of PCIe.
 
705 Up to PCIe Gen 4 (16 GT/s) support <> 745 Up to PCIe Gen 5 (32 GT/s) support
706 Connector is electrically compatible with PCIe Gen 5 (32 GT/s)      
 
723 Up to PCIe Gen 4 (16 GT/s) support <> 762 Up to PCIe Gen 5 (32 GT/s) support
724 Connector is electrically compatible with PCIe Gen 5 (32 GT/s)      
 
752 OCP NIC 3.0 provides two fundamental form factor options: a SFF (76 mm x 115 mm) and a LFF (139 mm x 115 mm). <> 790 OCP NIC 3.0 provides three fundamental form factor options: SFF (76 mm x 115 mm x 11.50 mm), TSFF (76 mm x 115 mm x 14.20 mm) and LFF (139 mm x 115 mm x 11.50 mm).
 
754 The SFF uses the Primary 4C+ connector to provide up to a x16 PCIe interface to the host. The additional 28-pin OCP bay carries sideband management interfaces as well as OCP NIC 3.0 specific control signals for multi-host PCIe support. The SFF card provides sufficient faceplate area to accommodate up to 2x QSFP modules, 4x SFP modules, or 4x RJ45 for BASE-T operation. The SFF supports up to 80 W of delivered power to the card edge. An example SFF is shown in Figure 1. <> 792 The SFF uses the Primary 4C+ connector to provide up to a x16 PCIe interface to the host. The additional 28-pin OCP bay carries sideband management interfaces as well as OCP NIC 3.0 specific control signals for multi-host PCIe support. The SFF card provides sufficient faceplate area to accommodate up to 2x QSFP modules, 4x SFP modules, or 4x RJ45 for BASE-T operation. The SFF and TSFF supports up to 80 W of delivered power to the card edge. Actual cooling capacity for a SFF and TSFF card is dependent on the ambient conditions over the NIC. An example SFF is shown in Figure 1. An Example TSFF is shown in Figure 2.
755 The LFF uses the Primary 4C+ connector to provide the same functionality as the SFF along with an additional Secondary 4C connector to provide up to a x32 PCIe interface. The LFF Card may utilize both the Primary and Secondary Connectors, or just the Primary Connector for lower PCIe lane count applications. Table 6 summarizes the LFF permutations. The LFF supports higher power envelopes and provides additional board area for more complex designs. The LFF supports up to 150 W of delivered power to the card edge across the two connectors. An example LFF is shown in Figure 2.   793 The LFF uses the Primary 4C+ connector to provide the same functionality as the SFF along with an additional Secondary 4C connector to provide up to a x32 PCIe interface. The LFF Card may utilize both the Primary and Secondary Connectors, or just the Primary Connector for lower PCIe lane count applications. Table 6 summarizes the LFF permutations. The LFF supports higher power envelopes and provides additional board area for more complex designs. The LFF supports up to 150 W of delivered power to the card edge across the two connectors. Actual cooling capacity for the LFF is dependent on the ambient conditions over the NIC. An example LFF is shown in Figure 3.
756 For LFF Cards, implementations may use both the Primary and Secondary Connector (as shown in Figure 4), or may use the Primary Connector only (as shown in Figure 5) for the card edge gold fingers.   794 For LFF Cards, implementations may use both the Primary and Secondary Connector (as shown in Figure 5), or may use the Primary Connector only (as shown in Figure 6) for the card edge gold fingers.
757 Figure 4: Primary Connector (4C+) and Secondary Connector (4C) (LFF) OCP NIC 3.0 Cards   795 Figure 5: Primary Connector (4C+) and Secondary Connector (4C) (LFF) OCP NIC 3.0 Cards
758 Figure 5: Primary Connector (4C+) Only (LFF) OCP NIC 3.0 Cards   796 Figure 6: Primary Connector (4C+) Only (LFF) OCP NIC 3.0 Cards
759 For both form factors, an OCP NIC 3.0 card may optionally implement a subset of pins to support less than a x16 PCIe connection. This may be implemented using a 2C+ card edge per SFF-TA-1002. The baseboard Primary Connector shall use a 4C+ in all cases. Figure 6 illustrates the supported 4C+ and 2C+ card edge configurations on a 4C+ Primary Connector.   797 For both form factors, an OCP NIC 3.0 card may optionally implement a subset of pins to support less than a x16 PCIe connection. This may be implemented using a 2C+ card edge per SFF-TA-1002. The baseboard Primary Connector shall use a 4C+ in all cases. Figure 7 illustrates the supported 4C+ and 2C+ card edge configurations on a 4C+ Primary Connector.
760 Figure 6: Primary Connector (4C+) with 4C and 2C (SFF) OCP NIC 3.0 Cards   798 Figure 7: Primary Connector (4C+) with 4C and 2C (SFF) OCP NIC 3.0 Cards
761 Table 6 summarizes the supported card form factors. SFF cards support the Primary Connector and up to 16 PCIe lanes. LFF cards support implementations with both the Primary and Secondary Connectors and up to 32 PCIe lanes, or a Primary Connector only implementation with up to 16 PCIe lanes.   799 Table 6 summarizes the supported card form factors. SFF and TSFF cards support the Primary Connector and up to 16 PCIe lanes. LFF cards support implementations with both the Primary and Secondary Connectors and up to 32 PCIe lanes, or a Primary Connector only implementation with up to 16 PCIe lanes.
 
769 SFF (x8) <> 807 SFF,TSFF (x8)
 
773 SFF (x16) <> 811 SFF, TSFF (x16)
 
790 SFF Faceplate Configurations <> 828 SFF and TSFF Faceplate Configurations
791 The SFF configuration views are shown below. Three different faceplates are available for the SFF – a pull tab, ejector latch and an internal lock version are available. The same SFF OCP NIC 3.0 PBA assembly accepts all three faceplates types and may be interchanged depending on the end application. The drawings shown in Figure 7 below illustrate a representative front, side and top views of the SFF.   829 The SFF and TSFF configuration views are shown below. Three different faceplates are each available for the SFF and TSFF – pull tab, ejector latch and internal lock. The same SFF and TSFF OCP NIC 3.0 PBA accepts up to six faceplate types depending on the end application. Faceplates are attached to the PCBA at the time of manufacture. A TSFF faceplate may be used on a SFF PBA. The drawings shown in Figure 8 below illustrates representative ¾ views of the SFF only, front, side and top views of SFF and TSFF implementations.
      830 Note: The TSFF implementation uses the same PCB outline as SFF. The faceplate and top-side Z-height envelope grows to 14.20 mm. Additional I/O connector options are available with the TSFF.
792 Where space is permitted on the faceplate, square vents sized to a maximum of 3.0 mm x 3.0 mm must be added to help optimize airflow while maintaining the integrity of the faceplate structure. EMI considerations should also be taken into account during the design process. Refer to the images shown in Figure 8 for example square vent configurations depending on the line side I/O connectors.   831 Where space is permitted on the faceplate, square vents sized to a maximum of 3.0 mm x 3.0 mm may be added to help optimize airflow while maintaining the integrity of the faceplate structure. EMI mitigation should also be considered during the design process. Refer to the images shown in Figure 9 for example square vent configurations depending on the line side I/O connectors.
793 Depending on the OCP NIC 3.0 card implementation, I/O connectors may be placed anywhere within the allowable connector keep in regions as defined by the SFF PBA mechanical drawings and faceplate drawings of Section 2.5.1.   832 Depending on the OCP NIC 3.0 card implementation, I/O connectors may be placed anywhere within the allowable connector keep in regions as defined by the SFF and TSFF PBA mechanical drawings and faceplate drawings of Section 2.5.1 and Section 2.5.2.
794 The OCP NIC 3.0 outline provides an optional feature to lock the card into the chassis. This is accomplished with two notches – one on each side of the card guide rail. A baseboard may choose to use one or both notches for the internal locking mechanism. The OCP NIC 3.0 outline provides a notch location on both guide rails to provide flexible configurations to baseboard vendors. If a locking feature is implemented on the baseboard, the OCP NIC 3.0 card may only be inserted or removed after actuating the internal locking mechanism. These retention notches are compatible with all chassis implementations. Please refer to the SFF dimensions in Section 2.5.1 for details. The internal locking mechanism is not available on LFF cards.   833 The OCP NIC 3.0 outline provides an optional feature to lock the card into the chassis. This is accomplished with two notches – one on each side of the card guide rail. A baseboard may choose to use one or both notches for the internal locking mechanism. The OCP NIC 3.0 outline provides a notch location on both guide rails to provide flexible configurations to baseboard vendors. If a locking feature is implemented on the baseboard, the OCP NIC 3.0 card may only be inserted or removed after actuating the internal locking mechanism. The PCB retention notches are compatible with all chassis implementations. Please refer to the SFF dimensions in Section 2.5.1 for details. The internal locking mechanism is not available on LFF cards.
795 Note: The OCP NIC 3.0 card supplier shall add port identification on the faceplate assembly that meet their manufacturing and customer requirements.   834 Note: The OCP NIC 3.0 card supplier may add port identification on the faceplate assembly that meet their manufacturing and customer requirements.
 
797 Figure 7: SFF NIC Configuration Views <> 836 Figure 8: SFF/TSFF NIC Configuration Views
 
801 Front View <> 840 Front View (SFF)
802 Side View   841 Side View (SFF)
      842 Front View (TSFF)
      843 Side View (TSFF)
 
804 Figure 8 illustrates example SFF 3D views for the supported line side I/O implementations. The line side I/O implementations are discussed in Section 2.2. <> 845 Figure 9 illustrates example SFF 3D views for the supported line side I/O implementations. The line side I/O implementations are discussed in Section 2.2. TSFF implementations are similar but have a taller faceplate.
805 Figure 8: SFF NIC Line Side 3D Views   846 Figure 9: SFF NIC Line Side 3D Views
 
812 Figure 9 illustrates example SFF 3D views of the pull tab and ejector latch assemblies mounted in a chassis utilizing a straddle mount connector and a right-angle connector. The baseboard connector options are discussed in Section 3.2. The SFF OCP NIC 3.0 card is identical for both chassis connector options. <> 853 Figure 10 illustrates example SFF 3D views of the pull tab and ejector latch assemblies mounted in a chassis utilizing a straddle mount connector and a right-angle connector. The baseboard connector options are discussed in Section 3.2. The SFF OCP NIC 3.0 card is identical for both chassis connector options.
 
815 Figure 9: SFF NIC Chassis Mounted 3D Views <> 856 Figure 10: SFF NIC Chassis Mounted 3D Views
 
823 The LFF configuration views are shown below. A single faceplate implementation is available for the LFF – with a single ejector latch. The long ejector is the default configuration, however, a short ejector version is available for non-shadowed front I/O configurations and is being considered for future development. Similar to the SFF, if additional LFF faceplate implementations become available, the same LFF OCP NIC 3.0 PBA assembly shall be able to accept new faceplate types and may be interchanged depending on the end application. The drawings shown in Figure 10 below illustrate a representative front, side and top views of the LFF. <> 864 The LFF configuration views are shown below. A single faceplate implementation is available for the LFF – with a single ejector latch. The long ejector is the default configuration, however, a short ejector version is available for non-shadowed front I/O configurations and is being considered for future development. Like the SFF and TSFF, if additional LFF faceplate implementations become available, the same LFF OCP NIC 3.0 PBA accepts up to three faceplate types depending on the end application. Faceplates are attached to the PCBA at the time of manufacture. The drawings shown in Figure 11 below illustrate a representative front, side and top views of the LFF.
824 Where space is permitted on the faceplate, square vents sized to a maximum of 3.0 mm x 3.0 mm must be added to help optimize airflow while maintaining the integrity of the faceplate structure. EMI considerations should also be taken into account during the design process. Refer to the images shown in Figure 11 for example square vent configurations depending on the line side I/O connectors.   865 Where space is permitted on the faceplate, square vents sized to a maximum of 3.0 mm x 3.0 mm may be added to help optimize airflow while maintaining the integrity of the faceplate structure. EMI considerations should also be considered during the design process. Refer to the images shown in Figure 12 for example square vent configurations depending on the line side I/O connectors.
 
828 Figure 10: LFF NIC Configuration Views <> 869 Figure 11: LFF NIC Configuration Views
 
833 Figure 11 illustrates example LFF 3D views for the supported line side I/O implementations. The line side I/O implementations are discussed in Section 2.2. <> 874 Figure 12 illustrates example LFF 3D views for the supported line side I/O implementations. The line side I/O implementations are discussed in Section 2.2.
834 Figure 11: LFF NIC Line Side 3D Views   875 Figure 12: LFF NIC Line Side 3D Views
 
844 Figure 12 illustrates example LFF 3D views of the ejector latch assembly mounted in a chassis utilizing a straddle mount connector and a right-angle connector. The baseboard connector options are discussed in Section 3.2. The LFF OCP NIC 3.0 card is identical for both chassis connector options. <> 885 Figure 13 illustrates example LFF 3D views of the ejector latch assembly mounted in a chassis utilizing a straddle mount connector and a right-angle connector. The baseboard connector options are discussed in Section 3.2. The LFF OCP NIC 3.0 card is identical for both chassis connector options.
845 Figure 12: LFF NIC Chassis Mounted 3D Views   886 Figure 13: LFF NIC Chassis Mounted 3D Views
 
852 At the time of this writing, the SFF and LFF implementations have been optimized to support the standard line side I/O implementations shown in Table 7. OCP NIC 3.0 cards may implement a subset of line side connectors and shall stay within the allowed I/O area as depicted in Section 2.4.3 for SFF and Section 2.4.4 for LFF. <> 893 At the time of this writing, the SFF, TSFF and LFF implementations have been optimized to support the standard line side I/O implementations shown in Table 7. OCP NIC 3.0 cards may implement a subset of line side connectors and shall stay within the allowed I/O area as depicted in Section 2.4.3 for SFF, Section 2.4.4 for TSFF and Section 2.4.5 for LFF.
 
856 SFF <> 897 SFF, TSFF
857 2x QSFP+/QSFP28   898 2x QSFP+/QSFP28/QSFP-DD
858 SFF   899 SFF, TSFF
 
860 SFF <> 901 SFF, TSFF
 
    -+ 903 TSFF
      904 1x OSFP-RHS
      905 TSFF
      906 2x QSFP-DD
 
    -+ 928 OSFP-RHS
      929 OSFP MSA
      930 OSFP management Interface Specification
 
    -+ 940 QSFP-DD
      941 QSFP-DD MSA
      942 CMIS 5.0
 
893 Additional combinations and connector types (such as SFP-DD and QSFP-DD) are permissible as I/O form factor technologies and thermal capabilities evolve. <> 944 Additional combinations and connector types are permissible as I/O form factor technologies and thermal capabilities evolve.
894 Top Level Assembly (SFF and LFF)   945 Top Level Assembly (SFF, TSFF and LFF)
895 The images in Figure 13 illustrate the exploded top-level assemblies for both the SFF and the LFF.   946 The images in Figure 14 illustrate the exploded top-level assemblies for SFF, TSFF and LFF. 
      947 Note: The TSFF implementation uses the same PCB outline as SFF. The faceplate and top-side Z-height envelope grows to 14.20 mm. Refer to the faceplate subassembly drawings in Section 2.4 for more details.
896 Figure 13: PBA Exploded Views (SFF and LFF)   948 Figure 14: PBA Exploded Views (SFF, TSFF and LFF)
 
    -+ 950 TSFF with Pull Tab
 
    -+ 953 TSFF with Ejector Latch
 
    -+ 955 TSFF with Internal Lock
 
905 Faceplate Subassembly (SFF and LFF) <> 962 Faceplate Subassembly (SFF, TSFF and LFF)
906 The following section define the generic SFF and LFF faceplates.   963 The following section define the generic SFF, TSFF and LFF faceplates.
 
908 The images in Figure 14 illustrate the three faceplates subassemblies as exploded views. The bill of materials is shown in Section 2.4.2. <> 965 The images in Figure 15 illustrate the three faceplates subassemblies as exploded views. The bill of materials is shown in Section 2.4.2.
909 Figure 14: Faceplate Assembly Exploded Views (SFF and LFF)   966 Figure 15: Faceplate Assembly Exploded Views (SFF, TSFF and LFF)
910 SFF with Pull Tab   967 SFF, TSFF with Pull Tab
911 SFF with Ejector Latch   968 SFF, TSFF with Ejector Latch
912 SFF with Internal Lock   969 SFF, TSFF with Internal Lock
 
915 Table 9 shows the bill of materials for the SFF and LFF assemblies. Item number call outs align with the SFF and LFF numbering of Figure 14. <> 972 Table 9 shows the bill of materials for the SFF, TSFF and LFF assemblies. Item number call outs align with the SFF, TSFF and LFF numbering of Figure 15.
 
    -+ 982 1E
      983 1F
      984 1G
 
930 NIC_OCPv3_SFF_Faceplate_Latch_20190719.pdf <> 990 NIC_OCPv3_TSFF_Faceplate_Pulltab_20210527.pdf
 
    -+ 992 NIC_OCPv3_SFF_Faceplate_Latch_20190719.pdf
      993 1D
      994 NIC_OCPv3_TSFF_Faceplate_Latch_20210527.pdf
      995 1E
 
    -+ 997 1F
      998 NIC_OCPv3_TSFF_Faceplate_IntLatch_20210527.pdf
 
934 1D <> 1000 1G
 
965 4 <> 1031 4A
      1032 4B
 
    <> 1034 4A
967 LT18DP1911   1035 LT18DP1911 (for SFF, LFF)
      1036 4B
      1037 LT21DP2320 (for TSFF)
 
979 See Section 2.4.8 and drawing <> 1049 See Section 2.4.9 and drawing
 
985 SFF Ejector: See Section 2.4.5 and drawing <> 1055 SFF Ejector: See Section 2.4.6 and drawing
 
989 LFF Ejector: See Section 2.4.6 & Drawing <> 1059 LFF Ejector: See Section 2.4.7 & Drawing
 
996 See Section 2.4.7 and drawing <> 1066 See Section 2.4.8 and drawing
 
1017 SFF Generic I/O Faceplate <> 1087 SFF Generic I/O Faceplates
1018 Figure 15 shows the standard SFF I/O bracket with a thumbscrew and pull-tab assembly.   1088 Figure 16 shows the standard SFF I/O bracket with a thumbscrew and pull-tab assembly.
1019 Figure 15: SFF Generic I/O Faceplate with Pulltab Version (2D View)   1089 Figure 16: SFF Generic I/O Faceplate – Pull Tab Version (2D View)
1020 Figure 16: SFF Generic I/O Faceplate – Ejector Version (2D View)   1090 Figure 17: SFF Generic I/O Faceplate – Ejector Version (2D View)
1021 Figure 17: SFF Generic I/O Faceplate – Internal Lock Version (2D View)   1091 Figure 18: SFF Generic I/O Faceplate – Internal Lock Version (2D View)
      1092 TSFF Generic I/O Faceplates
      1093 The TSFF diagrams call out the deltas from the SFF diagrams. Refer to the SFF diagrams in Section 2.4.3 for the remaining details. 
      1094 Figure 19: TSFF Generic I/O Faceplate – Pull Tab Version (2D View)
      1095 Figure 20: TSFF Generic I/O Faceplate – Ejector Version (2D View)
      1096 Figure 21: TSFF Generic I/O Faceplate – Internal Lock Version (2D View)
 
1023 Figure 18: LFF Generic I/O Faceplate – Ejector Version (2D View) <> 1098 Figure 22: LFF Generic I/O Faceplate – Ejector Version (2D View)
1024 Ejector Lever (SFF)   1099 Ejector Lever (SFF, TSFF)
 
1026 Figure 19: SFF I/O Faceplate – Ejector Lever (2D View) <> 1101 Figure 23: SFF I/O Faceplate – Ejector Lever (2D View)
 
1029 Figure 20: LFF I/O Faceplate – Ejector Lever (2D View) <> 1104 Figure 24: LFF I/O Faceplate – Ejector Lever (2D View)
1030 Ejector Lock (SFF and LFF)   1105 Ejector Lock (SFF, TSFF and LFF)
1031 The SFF and LFF ejector uses a locking mechanism at the end of the handle to retain the lever position. This is shown in Figure 21.   1106 The SFF and LFF ejector uses a locking mechanism at the end of the handle to retain the lever position. This is shown in Figure 25.
1032 Figure 21: Ejector Lock   1107 Figure 25: Ejector Lock
 
1034 The SFF and LFF card ejector handle uses a clinch nut as a spacer and rotation anchor. The clinch nut binds the ejector handle to the faceplate. Two clinch nut options are available to accommodate supplier manufacturing processes. These are shown in Figure 22 and Figure 23. <> 1109 The SFF/TSFF and LFF card ejector handle uses a clinch nut as a spacer and rotation anchor. The clinch nut binds the ejector handle to the faceplate. Two clinch nut options are available to accommodate supplier manufacturing processes. These are shown in Figure 26 and Figure 27.
1035 Figure 22: Clinch Nut Option A   1110 Figure 26: Clinch Nut Option A
1036 Figure 23: Clinch Nut Option B   1111 Figure 27: Clinch Nut Option B
 
    <> 1114 Note: The SFF top, detail and bottom view keep out zones are also applicable to the TSFF.
1039 Figure 24: SFF Keep Out Zone – Top View   1115 Figure 28: SFF Keep Out Zone – Top View
 
1041 Figure 25: SFF Keep Out Zone – Top View – Detail A <> 1117 Figure 29: SFF Keep Out Zone – Top View – Detail A
1042 Figure 26: SFF Keep Out Zone – Bottom View   1118 Figure 30: SFF Keep Out Zone – Bottom View
 
1044 Figure 27: SFF Keep Out Zone – Side View <> 1120 Figure 31: SFF Keep Out Zone – Side View
 
1046 Figure 28: SFF Keep Out Zone – Side View – Detail D <> 1122 Figure 32: SFF Keep Out Zone – Side View – Detail D
      1123 TSFF Keep Out Zones
      1124 The TSFF keep out zones are identical to the SFF except for the side view. This is shown in Figure 33. Refer to the SFF keep out zone in Section 2.5.1 for the remaining details. 
      1125 Figure 33: TSFF Keep Out Zone – Side View
 
1048 Figure 29: LFF Keep Out Zone – Top View <> 1127 Figure 34: LFF Keep Out Zone – Top View
 
1050 Figure 30: LFF Keep Out Zone – Top View – Detail A <> 1129 Figure 35: LFF Keep Out Zone – Top View – Detail A
 
1052 Figure 31: LFF Keep Out Zone – Bottom View <> 1131 Figure 36: LFF Keep Out Zone – Bottom View
1053 Figure 32: LFF Keep Out Zone – Side View   1132 Figure 37: LFF Keep Out Zone – Side View
1054 Figure 33: LFF Keep Out Zone – Side View – Detail D   1133 Figure 38: LFF Keep Out Zone – Side View – Detail D
 
1056 Refer to the 3D CAD files for the baseboard keep out zones for both the SFF and LFF designs. The 3D CAD files are available for download on the OCP NIC 3.0 Wiki: http://www.opencompute.org/wiki/Server/Mezz <> 1135 Refer to the 3D CAD files for the baseboard keep out zones for the SFF, TSFF and LFF designs. The 3D CAD files are available for download on the OCP NIC 3.0 Wiki: http://www.opencompute.org/wiki/Server/Mezz
 
1058 All OCP NIC 3.0 cards shall implement an insulator to prevent the bottom side card components from shorting out to the baseboard chassis. The recommended insulator thickness is 0.25 mm and shall reside within the following mechanical envelope for the SFF and LFF. An alternate insulator thickness of 0.127 mm is permitted. The total stack up height of the secondary side components, insulator and the labels shall not exceed the 2 mm keep-in dimension as shown in Section 2.7.1 and 2.7.2. <> 1137 All OCP NIC 3.0 cards shall implement an insulator to prevent the bottom side card components from shorting out to the baseboard chassis. The recommended insulator thickness is 0.25 mm and shall reside within the following mechanical envelopes for the SFF, TSFF and LFF. An alternate insulator thickness of 0.127 mm is permitted. The total stack up height of the secondary side components, insulator and the labels shall not exceed the 2 mm keep-in dimension as shown in Section 2.7.1 and 2.7.2.
 
1060 SFF Insulator <> 1139 SFF, TSFF Insulator
1061 Figure 34: SFF Bottom Side Insulator (3D View)   1140 Figure 39: SFF, TSFF Bottom Side Insulator (3D View)
 
1063 Figure 35: SFF Bottom Side Insulator (Top and Side View) <> 1142 Figure 40: SFF, TSFF Bottom Side Insulator (Top and Side View)
1064 Figure 36: SFF Bottom Side Insulator (alternate) (Top and Side View)   1143 Figure 41: SFF, TSFF Bottom Side Insulator (alternate) (Top and Side View)
 
1066 Figure 37: LFF Bottom Side Insulator (3D View) <> 1145 Figure 42: LFF Bottom Side Insulator (3D View)
1067 Figure 38: LFF Bottom Side Insulator (Top and Side View)   1146 Figure 43: LFF Bottom Side Insulator (Top and Side View)
1068 Figure 39: LFF Bottom Side Insulator (alternate) (Top and Side View)   1147 Figure 44: LFF Bottom Side Insulator (alternate) (Top and Side View)
1069 Critical-to-Function (CTF) Dimensions (SFF and LFF)   1148 Critical-to-Function (CTF) Dimensions (SFF, TSFF and LFF)
 
1071 The following CTF tolerances are used in this section and are the same for both the SFF and LFF. <> 1150 The following CTF tolerances are used in this section and are the same for the SFF, TSFF and LFF.
1072 Table 10: CTF Default Tolerances (SFF and LFF OCP NIC 3.0)   1151 Table 10: CTF Default Tolerances (SFF, TSFF and LFF OCP NIC 3.0)
 
1075 Figure 40: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View) <> 1154 Figure 45: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View)
1076 Figure 41: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View)   1155 Figure 46: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View)
1077 Figure 42: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View)   1156 Figure 47: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View)
 
1080 Figure 43: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View) <> 1159 Figure 48: SFF OCP NIC 3.0 Card with Ejector Latch CTF Dimensions (Top View)
1081 Figure 44: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)   1160 Figure 49: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)
1082 Figure 45: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)   1161 Figure 50: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)
 
1085 Figure 46: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View) <> 1164 Figure 51: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View)
1086 Figure 47: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Front View)   1165 Figure 52: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Front View)
1087 Figure 48: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Side View)   1166 Figure 53: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Side View)
 
1091 Figure 49: SFF Baseboard Chassis CTF Dimensions (Rear View) <> 1170 Figure 54: SFF Baseboard Chassis CTF Dimensions (Rear View)
1092 Figure 50: SFF Baseboard Chassis to Card Thumb Screw CTF Dimensions (Side View)   1171 Figure 55: SFF Baseboard Chassis to Card Thumb Screw CTF Dimensions (Side View)
1093 Figure 51: SFF Baseboard Chassis to Ejector lever Card CTF Dimensions (Side View)   1172 Figure 56: SFF Baseboard Chassis to Ejector lever Card CTF Dimensions (Side View)
1094 Figure 52: SFF Baseboard Chassis CTF Dimensions (Rear Rail Guide View)   1173 Figure 57: SFF Baseboard Chassis CTF Dimensions (Rear Rail Guide View)
 
1095 Figure 53: SFF Baseboard Chassis CTF Dimensions (Rail Guide Detail) – Detail C <> 1175 Figure 58: SFF Baseboard Chassis CTF Dimensions (Rail Guide Detail) – Detail C
 
    -+ 1177 TSFF Pull Tab CTF Dimensions
      1178 The TSFF CTF dimensions only differ for the Z-height envelope and are noted below. Refer to the corresponding SFF drawing for the remaining dimensions.
      1179 Figure 59: TSFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View)
      1180 TSFF Ejector Latch CTF Dimensions
      1181 The TSFF CTF dimensions only differ for the Z-height envelope and are noted below. Refer to the corresponding SFF drawing for the remaining dimensions.
      1182 Figure 60: TSFF OCP NIC 3.0 Card with Ejector Latch CTF Dimensions (Top View)
      1183 TSFF Internal Lock CTF Dimensions
      1184 The TSFF CTF dimensions only differ for the Z-height envelope and are noted below. Refer to the corresponding SFF drawing for the remaining dimensions.
      1185 Figure 61: TSFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View)
      1186 TSFF Baseboard CTF Dimensions
      1187 The TSFF CTF dimensions only differ for the Z-height envelope and are noted below. Refer to the corresponding SFF drawing for the remaining dimensions.
      1188 Figure 62: TSFF Baseboard Chassis CTF Dimensions (Rear View)
 
1099 Figure 54: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View) <> 1191 Figure 63: LFF OCP NIC 3.0 Card with Ejector Latch CTF Dimensions (Top View)
1100 Figure 55: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)   1192 Figure 64: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)
1101 Figure 56: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)   1193 Figure 65: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)
 
1105 Figure 57: LFF Baseboard Chassis CTF Dimensions (Rear View) <> 1197 Figure 66: LFF Baseboard Chassis CTF Dimensions (Rear View)
 
1107 Figure 58: LFF Baseboard Chassis CTF Dimensions (Side View) <> 1199 Figure 67: LFF Baseboard Chassis CTF Dimensions (Side View)
1108 Figure 59: LFF Baseboard Chassis CTF Dimensions (Rail Guide View)   1200 Figure 68: LFF Baseboard Chassis CTF Dimensions (Rail Guide View)
1109 Figure 60: LFF Baseboard Chassis CTF Dimensions (Rail Guide – Detail C)   1201 Figure 69: LFF Baseboard Chassis CTF Dimensions (Rail Guide – Detail C)
1110 The right angle and straddle mount card guides are identical between the SFF and LFF. The card guide models are included in the 3D CAD packages and may be downloaded from the OCP NIC 3.0 Wiki site: http://www.opencompute.org/wiki/Server/Mezz.   1202 The right angle and straddle mount card guides are identical between the SFF, TSFF and LFF. The card guide models are included in the 3D CAD packages and may be downloaded from the OCP NIC 3.0 Wiki site: http://www.opencompute.org/wiki/Server/Mezz.
 
1123 Figure 61: SFF Label Area Example <> 1215 Figure 70: SFF, TSFF Label Area Example
 
1152 As an example, the label content of a quad SFP OCP NIC 3.0 card with a single management MAC address shall be constructed to show human readable data per the Label Data column of Table 11. The constructed label is shown in Figure 62. For each human readable line, there is a MAC prefix “Px:” for a line side Port, or “MEx:" for a managed controller instance, followed by the MAC address. The port/controller association for each row is shown in the far right column. <> 1244 As an example, the label content of a quad SFP OCP NIC 3.0 card with a single management MAC address shall be constructed to show human readable data per the Label Data column of Table 11. The constructed label is shown in Figure 71. For each human readable line, there is a MAC prefix “Px:” for a line side Port, or “MEx:" for a managed controller instance, followed by the MAC address. The port/controller association for each row is shown in the far right column.
 
1178 Figure 62: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller <> 1270 Figure 71: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller
 
1180 As a second example, the label content of an octal port (2xQSFP with “breakout” support) OCP NIC 3.0 card with two managed silicon instances is constructed per Table 12. The constructed label is shown in Figure 63. The MAC address label shall also list the four MAC addresses associated with QSFP lanes [1:4] for QSFP connectors that allow “breakout” modes. The Host-MAC address presentation may also be formatted horizontally for easier readability. <> 1272 As a second example, the label content of an octal port (2xQSFP with “breakout” support) OCP NIC 3.0 card with two managed silicon instances is constructed per Table 12. The constructed label is shown in Figure 72. The MAC address label shall also list the four MAC addresses associated with QSFP lanes [1:4] for QSFP connectors that allow “breakout” modes. The Host-MAC address presentation may also be formatted horizontally for easier readability.
 
1226 Figure 63: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller <> 1318 Figure 72: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller
 
1228 For multi-host implementations, each MAC address shall be prefixed with the host association “Hx” prior to the port number, where x represents the host number. An example of this is shown in Table 13 and Figure 64. <> 1320 For multi-host implementations, each MAC address shall be prefixed with the host association “Hx” prior to the port number, where x represents the host number. An example of this is shown in Table 13 and Figure 73.
 
1265 Figure 64: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers <> 1357 Figure 73: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers
 
1267 The following example shows a single port device with quad hosts. To conserve space on the MAC address label, this example only shows the MAC addresses for Port 1 through Port 4. The MAC address for each managed host is Px+1. This is shown in Table 14 and Figure 65. <> 1359 The following example shows a single port device with quad hosts. To conserve space on the MAC address label, this example only shows the MAC addresses for Port 1 through Port 4. The MAC address for each managed host is Px+1. This is shown in Table 14 and Figure 74.
 
1314 Figure 65: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller <> 1406 Figure 74: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller
 
1337 Figure 66: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller <> 1429 Figure 75: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller
1338 Figure 66 illustrates the use of ellipses in the human readable text to individually indicate a range of Port and Management MAC addresses. In this example, the 2D data matrix shall contain all 16 MAC addresses.   1430 Figure 75 illustrates the use of ellipses in the human readable text to individually indicate a range of Port and Management MAC addresses. In this example, the 2D data matrix shall contain all 16 MAC addresses.
 
    -+ 1449 TSFF generic faceplate assembly
      1450 TSFF_Pull_Tab_20210527.stp
      1451 TSFF_Latch_20210527.stp
      1452 TSFF_Internal_Latch_20210527.Stp
 
1368 SFF cards fit in the Primary Connector. Primary Connector compliant cards are 76 mm x 115 mm and may implement the full 168-pins. The Primary Connector cards may optionally implement a subset of gold finger pins if there is a reduced PCIe width requirement (such as 1 x8 and below). In this case, the card edge gold finger may implement a 2C+ design. The overall board thickness is 1.57 mm. The gold finger dimensions for the Primary Connector compliant cards are shown below. <> 1464 SFF and TSFF cards fit in the Primary Connector. Primary Connector compliant cards are 76 mm x 115 mm and may implement the full 168-pins. The Primary Connector cards may optionally implement a subset of gold finger pins if there is a reduced PCIe width requirement (such as 1 x8 and below). In this case, the card edge gold finger may implement a 2C+ design. The overall board thickness is 1.57 mm. The gold finger dimensions for the Primary Connector compliant cards are shown below.
 
1371 Figure 67: SFF Primary Connector Gold Finger Dimensions – x16 – Top Side (“B” Pins) <> 1467 Figure 76: SFF, TSFF Primary Connector Gold Finger Dimensions – x16 – Top Side (“B” Pins)
1372 Figure 68: SFF Primary Connector Card Profile Dimensions   1468 Figure 77: SFF, TSFF Primary Connector Card Profile Dimensions
1373 Figure 69: SFF Primary Conector Gold Finger - Detail D   1469 Figure 78: SFF, TSFF Primary Conector Gold Finger - Detail D
1374 Figure 70: LFF Gold Finger Dimensions – x32 – Top Side (“B” Pins)   1470 Figure 79: LFF Gold Finger Dimensions – x32 – Top Side (“B” Pins)
1375 Figure 71: LFF Gold Finger Dimensions – x32 – Bottom Side (“A” Pins)   1471 Figure 80: LFF Gold Finger Dimensions – x32 – Bottom Side (“A” Pins)
 
2024 The OCP NIC 3.0 connectors are compliant to the 4C+ and 4C connectors as defined in the SFF-TA-1002 specification for a right angle or straddle mount form factor. The Primary Connector is a 4C+ implementation with 168-pins. The Secondary Connector is a 4C implementation with 140-pins. Both the Primary and Secondary Connectors includes support for up to 32 differential pairs to support a x16 PCIe connection. Each connector also provides 6 pins of +12V_EDGE, and 1 pin of +3.3V_EDGE for power. This implementation is common between both the Primary and Secondary Connectors. In addition, the 4C+ implementation of the Primary Connector has a 28-pin OCP Bay used for management and support for up to a 4 x2 and 4 x4 multi-host configuration on the Primary Connector. The Primary and Secondary Connector drawings are shown below. <> 2120 The OCP NIC 3.0 connectors are compliant to the 4C+ and 4C connectors as defined in the SFF-TA-1002 specification for a right angle or straddle mount form factor. The Primary Connector is a 4C+ implementation with 168-pins. The Secondary Connector is a 4C implementation with 140-pins. Both the Primary and Secondary Connectors includes support for up to 32 differential pairs to support a x16 PCIe connection. Each connector also provides 6 pins of +12V_EDGE, and 1 pin of +3.3V_EDGE for power. This implementation is common between both the Primary and Secondary Connectors. In addition, the 4C+ implementation of the Primary Connector has a 28-pin OCP Bay used for management and support for up to a 4 x2 and 4 x4 multi-host configurations on the Primary Connector. The Primary and Secondary Connector drawings are shown below.
 
2041 Figure 72: 168-pin Base Board Primary Connector – Right Angle <> 2137 Figure 81: 168-pin Base Board Primary Connector – Right Angle
2042 Figure 73: 140-pin Base Board Secondary Connector – Right Angle   2138 Figure 82: 140-pin Base Board Secondary Connector – Right Angle
 
2044 The OCP NIC 3.0 right angle connectors have a 4.05 mm offset from the baseboard. This is shown in Figure 74. <> 2140 The OCP NIC 3.0 right angle connectors have a 4.05 mm offset from the baseboard. This is shown in Figure 83.
2045 Figure 74: OCP NIC 3.0 Card and Host Offset for Right Angle Connectors   2141 Figure 83: OCP NIC 3.0 Card and Host Offset for Right Angle Connectors
 
2077 Figure 75: 168-pin Base Board Primary Connector – Straddle Mount <> 2173 Figure 84: 168-pin Base Board Primary Connector – Straddle Mount
2078 Figure 76: 140-pin Base Board Secondary Connector – Straddle Mount   2174 Figure 85: 140-pin Base Board Secondary Connector – Straddle Mount
 
2080 The OCP NIC 3.0 straddle mount connectors have three baseboard PCB thicknesses they can accept. The available options are shown in Figure 77. The thicknesses are 0.062’’, 0.076’’, and 0.093’’. These PCBs must be controlled to a thickness of ±10%. These are available for both the Primary and Secondary Connector locations. At the time of this writing, the most commonly used part is expected to be the 0.076’’ baseboard thickness. <> 2176 The OCP NIC 3.0 straddle mount connectors have three baseboard PCB thicknesses they can accept. The available options are shown in Figure 86. The thicknesses are 0.062’’, 0.076’’, and 0.093’’. These PCBs must be controlled to a thickness of ±10%. These are available for both the Primary and Secondary Connector locations. At the time of this writing, the most used part is expected to be the 0.076’’ baseboard thickness.
2081 Figure 77: OCP NIC 3.0 Card and Baseboard PCB Thickness Options for Straddle Mount Connectors   2177 Figure 86: OCP NIC 3.0 Card and Baseboard PCB Thickness Options for Straddle Mount Connectors
2082 The connectors are capable of being used coplanar as shown in Figure 78. Additionally, the connectors are also capable of having a 0.3 mm offset from the centerline of the host board as shown in Figure 79.   2178 The connectors are capable of being used coplanar as shown in Figure 87. Additionally, the connectors are also capable of having a 0.3 mm offset from the centerline of the host board as shown in Figure 88.
2083 Figure 78: 0 mm Offset (Coplanar) for 0.062” Thick Baseboards   2179 Figure 87: 0 mm Offset (Coplanar) for 0.062” Thick Baseboards
2084 Figure 79: 0.3 mm Offset for 0.076” Thick Baseboards   2180 Figure 88: 0.3 mm Offset for 0.076” Thick Baseboards
 
2086 In order to support the LFF, systems must locate the Primary and Secondary Connectors per the mechanical drawing shown in Figure 80 and Figure 81. <> 2182 In order to support the LFF, systems must locate the Primary and Secondary Connectors per the mechanical drawing shown in Figure 89 and Figure 90.
2087 Figure 80: Primary and Secondary Connector Locations for LFF Support with Right Angle Connectors   2183 Figure 89: Primary and Secondary Connector Locations for LFF Support with Right Angle Connectors
2088 Figure 81: Primary and Secondary Connector Locations for LFF Support with Straddle Mount Connectors   2184 Figure 90: Primary and Secondary Connector Locations for LFF Support with Straddle Mount Connectors
 
2778 For baseboards, the PET[0:15] signals are required at the Primary Connector for a SFF slot. PET[0:15] and PET[16:31] are required for a LFF slot. <> 2874 For baseboards, the PET[0:15] signals are required at the Primary Connector for the SFF and TSFF slots. PET[0:15] and PET[16:31] are required for a LFF slot.
2779 For SFF OCP NIC 3.0 cards, the required PET[0:15] signals shall be connected to the endpoint silicon. For silicon that uses less than a x16 connection, the appropriate PET[0:15] signals shall be connected per the endpoint datasheet.   2875 For SFF and TSFF OCP NIC 3.0 cards, the required PET[0:15] signals shall be connected to the endpoint silicon. For silicon that uses less than a x16 connection, the appropriate PET[0:15] signals shall be connected per the endpoint datasheet.
 
2864 For baseboards, the PER[0:15] signals are required at the Primary Connector for a SFF slot. PER[0:15] and PER[16:31] are required for a LFF slot. <> 2960 For baseboards, the PER[0:15] signals are required at the Primary Connector for the SFF and TSFF slots. PER[0:15] and PER[16:31] are required for a LFF slot.
2865 For SFF OCP NIC 3.0 cards, the required PER[0:15] signals shall be connected to the endpoint silicon. For silicon that uses less than a x16 connection, the appropriate PER[0:15] signals shall be connected per the endpoint datasheet.   2961 For SFF and TSFF OCP NIC 3.0 cards, the required PER[0:15] signals shall be connected to the endpoint silicon. For silicon that uses less than a x16 connection, the appropriate PER[0:15] signals shall be connected per the endpoint datasheet.
 
    -+ 3056 For hosts with unused PERST[1:5]# signals, a 10 kΩ pull down resistor shall be provided by the baseboard for each unused pin.
 
2976 For baseboards, the PWRBRK0# pin shall be implemented and available on the Primary Connector for SFF slots. In addition, the PWRBRK1# pin shall be implemented on the Secondary connector for LFF slots. <> 3073 For baseboards, the PWRBRK0# pin shall be implemented and available on the Primary Connector for the SFF and TSFF slots. In addition, the PWRBRK1# pin shall be implemented on the Secondary connector for LFF slots.
 
2978 Note: The PWRBRK[0:1]# pins are only available for OCP NIC 3.0 cards that implement a SFF 4C+ edge connector or a LFF. For SFF cards that implement at 2C+ edge connection, the PWRBRK[0:1]# functionality is not available. <> 3075 Note: The PWRBRK[0:1]# pins are only available for OCP NIC 3.0 cards that implement a SFF/TSFF 4C+ edge connector or a LFF. For SFF/TSFF cards that implement at 2C+ edge connection, the PWRBRK[0:1]# functionality is not available.
 
2980 This section provides the pin assignments for the PCIe present and bifurcation control signals. The AC/DC specifications are defined in Section 3.11. Example connection diagrams are shown in Figure 82 and Figure 83. <> 3077 This section provides the pin assignments for the PCIe present and bifurcation control signals. The AC/DC specifications are defined in Section 3.11. Example connection diagrams are shown in Figure 91 and Figure 92.
 
2982 PRSNTB[3:0]# pins are available to each connector and are independent of each other. For the SFF, the baseboard shall only read the Primary Connector PRSNTB[3:0]# to determine the card type. For the LFF, the baseboard shall read both the Primary and Secondary connector PRSNTB[3:0]# pins to determine the card type. The card type matrix is discussed in Section 3.5. <> 3079 PRSNTB[3:0]# pins are available to each connector and are independent of each other. For the SFF and TSFF, the baseboard shall only read the Primary Connector PRSNTB[3:0]# to determine the card type. For the LFF, the baseboard shall read both the Primary and Secondary connector PRSNTB[3:0]# pins to determine the card type. The card type matrix is discussed in Section 3.5.
 
3015 For baseboards, the BIF[2:0]# pins shall be driven from the baseboard I/O hub on the rising edge of AUX_PWR_EN. This allows the baseboard to force the OCP NIC 3.0 card bifurcation. The baseboard may optionally pull the BIF[2:0]# signals to AUX_PWR_EN or to ground per the definitions described in Section 3.5 if no dynamic bifurcation configuration is required. The BIF[2:0]# pins shall be low until AUX_PWR_EN is asserted. <> 3112 For baseboards, the BIF[2:0]# pins shall be driven from the baseboard I/O hub on the rising edge of AUX_PWR_EN. This allows the baseboard to force the OCP NIC 3.0 card bifurcation. The baseboard may optionally pull the BIF[2:0]# signals to AUX_PWR_EN or to ground per the definitions described in Section 3.5 if no dynamic bifurcation configuration is required. The BIF[2:0]# pins shall be low until AUX_PWR_EN is asserted. The BIF[2:0]# pins shall remain static after AUX_PWR_EN is asserted. The pins are not allowed to change states when the OCP NIC 3.0 card is powered on.
3016 For baseboards that allow dynamic bifurcation, the BIF[2:0] pins are driven low prior to AUX_PWR_EN. The state of the BIF[2:0] pins are driven with the rising edge of AUX_PWR_EN when bifurcation is requested. Refer to Figure 82 for an example configuration.   3113 For baseboards that allow dynamic bifurcation, the BIF[2:0] pins are driven low prior to AUX_PWR_EN. The state of the BIF[2:0] pins are driven with the rising edge of AUX_PWR_EN when bifurcation is requested. Refer to Figure 91 for an example configuration.
3017 For baseboards with static bifurcation, the BIF pins that are intended to be a logical ‘1’ shall be connected to a pull up to AUX_PWR_EN. BIF pins that are a logical ‘0’ may be directly tied to ground. Refer to Figure 83 for an example configuration.   3114 For baseboards with static bifurcation, the BIF pins that are intended to be a logical ‘1’ shall be connected to a pull up to AUX_PWR_EN. BIF pins that are a logical ‘0’ may be directly tied to ground. Refer to Figure 92 for an example configuration.
 
3020 Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[2:0]#) <> 3117 Figure 91: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[2:0]#)
3021 Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[2:0]#)   3118 Figure 92: PCIe Present and Bifurcation Control Pins (Static BIF[2:0]#)
 
3023 This section provides the pin assignments for the SMBus interface signals. The AC/DC specifications are defined in the SMBus 2.0 specification. The SMBus interface is pinned out on the Primary and Secondary Connectors. For SFF and LFF OCP NIC 3.0 card implementations, FRU and MCTP over SMBus transactions shall use the Primary Connector only. SMBus on the Secondary Connector may be a separate bus and is reserved for a future use case. An example connection diagram is shown in Figure 84. <> 3120 This section provides the pin assignments for the SMBus interface signals. The AC/DC specifications are defined in the SMBus 2.0 specification. The SMBus interface is pinned out on the Primary and Secondary Connectors. For SFF, TSFF and LFF OCP NIC 3.0 card implementations, FRU and MCTP over SMBus transactions shall use the Primary Connector only. SMBus on the Secondary Connector may be a separate bus and is reserved for a future use case. An example connection diagram is shown in Figure 93.
 
3047 Figure 84: Example SMBus Connections <> 3144 Figure 93: Example SMBus Connections
 
3050 This section provides the pin assignments for the NC-SI over RBT interface signals on the Primary Connector OCP bay. The AC/DC specifications for NC-SI over RBT are defined in the DMTF DSP0222 NC-SI specification. Example connection diagrams are shown in Figure 85 and Figure 86. <> 3147 This section provides the pin assignments for the NC-SI over RBT interface signals on the Primary Connector OCP bay. The AC/DC specifications for NC-SI over RBT are defined in the DMTF DSP0222 NC-SI specification. Example connection diagrams are shown in Figure 94 and Figure 95.
3051 Note: The RBT pins must provide the ability to be isolated on the baseboard side when AUX_PWR_EN=0 or when (AUX_PWR_EN=1 and NIC_PWR_GOOD=0). The RBT pins shall remain isolated until the power state machine has transitioned to Aux Power Mode or to Main Power Mode along with a valid indication of NIC_PWR_GOOD. This prevents a leakage path through unpowered silicon. The RBT REF_CLK must also be disabled until AUX_PWR_EN=1 and NIC_PWR_GOOD=1. Example buffering implementations are shown in Figure 85 and Figure 86. The isolator shall be controlled on the baseboard with a signal called RBT_ISOLATE#.   3148 Note: The RBT pins must provide the ability to be isolated on the baseboard side when AUX_PWR_EN=0 or when (AUX_PWR_EN=1 and NIC_PWR_GOOD=0). The RBT pins shall remain isolated until the power state machine has transitioned to Aux Power Mode or to Main Power Mode along with a valid indication of NIC_PWR_GOOD. This prevents a leakage path through unpowered silicon. The RBT REF_CLK must also be disabled until AUX_PWR_EN=1 and NIC_PWR_GOOD=1. Example buffering implementations are shown in Figure 94 and Figure 95. The isolator shall be controlled on the baseboard with a signal called RBT_ISOLATE#. The RBT_ISOLATE# signal shall remain asserted even when the NIC_PWR_GOOD signal is in the don’t care state. This is illustrated in Figure 116.
 
3103 If the baseboard supports multiple OCP NIC 3.0 cards connected to the same RBT interface, it shall implement logic that connects the RBT_ARB_OUT pin of the first populated OCP NIC 3.0 card to its RBT_ARB_IN pin if it is the only card present or to the RBT_ARB_IN pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic shall bypass slots that are not populated, powered off, or in ID mode. A two OCP NIC 3.0 card example using an analog mux is shown in Figure 86. <> 3200 If the baseboard supports multiple OCP NIC 3.0 cards connected to the same RBT interface, it shall implement logic that connects the RBT_ARB_OUT pin of the first populated OCP NIC 3.0 card to its RBT_ARB_IN pin if it is the only card present or to the RBT_ARB_IN pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic shall bypass slots that are not populated, powered off, or in ID mode. A two OCP NIC 3.0 card example using an analog mux is shown in Figure 95.
 
3105 For OCP NIC 3.0 cards that support hardware arbitration, this pin shall be connected between the card gold finger and the RBT_ARB_IN pin on the endpoint silicon. If the card implements two controllers, both must be connected internally to complete the ring, see Figure 86. If hardware arbitration is not supported, then this pin shall be directly connected to the card edge RBT_ARB_IN pin. This allows the hardware arbitration signals to pass through in a multi-Primary Connector baseboard. <> 3202 For OCP NIC 3.0 cards that support hardware arbitration, this pin shall be connected between the card gold finger and the RBT_ARB_IN pin on the endpoint silicon. If the card implements two controllers, both must be connected internally to complete the ring, see Figure 95. If hardware arbitration is not supported, then this pin shall be directly connected to the card edge RBT_ARB_IN pin. This allows the hardware arbitration signals to pass through in a multi-Primary Connector baseboard.
 
3110 If the baseboard supports multiple OCP NIC 3.0 cards connected to the same RBT interface, it shall implement logic that connects the RBT_ARB_IN pin of the first populated OCP NIC 3.0 card to its RBT_ARB_OUT pin if it is the only card present or to the RBT_ARB_OUT pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic shall bypass slots that are not populated, powered off, or in ID mode. A two OCP NIC 3.0 card example using an analog mux is shown in Figure 86. <> 3207 If the baseboard supports multiple OCP NIC 3.0 cards connected to the same RBT interface, it shall implement logic that connects the RBT_ARB_IN pin of the first populated OCP NIC 3.0 card to its RBT_ARB_OUT pin if it is the only card present or to the RBT_ARB_OUT pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic shall bypass slots that are not populated, powered off, or in ID mode. A two OCP NIC 3.0 card example using an analog mux is shown in Figure 95.
 
3112 For OCP NIC 3.0 cards that support hardware arbitration, this pin shall be connected between the card gold finger and the RBT_ARB_OUT pin on the endpoint silicon. If the card implements two controllers, both must be connected internally to complete the ring, see Figure 86. If hardware arbitration is not supported, then this pin shall be directly connected to the card edge RBT_ARB_OUT pin. This allows the hardware arbitration signals to pass through in a multi-Primary Connector baseboard. <> 3209 For OCP NIC 3.0 cards that support hardware arbitration, this pin shall be connected between the card gold finger and the RBT_ARB_OUT pin on the endpoint silicon. If the card implements two controllers, both must be connected internally to complete the ring, see Figure 95. If hardware arbitration is not supported, then this pin shall be directly connected to the card edge RBT_ARB_OUT pin. This allows the hardware arbitration signals to pass through in a multi-Primary Connector baseboard.
 
3142 Figure 85: NC-SI over RBT Connection Example – Single Primary Connector <> 3239 Figure 94: NC-SI over RBT Connection Example – Single Primary Connector
 
3144 Figure 86: NC-SI over RBT Connection Example – Dual Primary Connectors <> 3241 Figure 95: NC-SI over RBT Connection Example – Dual Primary Connectors
 
3146 Note 1: For baseboard designs with a single Primary Connector, connect ARB_IN to ARB_OUT to complete the NC-SI hardware arbitration ring. For designs with multiple Primary Connectors, connect ARB_IN and ARB_OUT to an analog mux to complete the NC-SI arbitration ring based on the number of cards installed in the system. An example dual Primary Connector implementation is shown in Figure 86. <> 3243 Note 1: For baseboard designs with a single Primary Connector, connect ARB_IN to ARB_OUT to complete the NC-SI hardware arbitration ring. For designs with multiple Primary Connectors, connect ARB_IN and ARB_OUT to an analog mux to complete the NC-SI arbitration ring based on the number of cards installed in the system. An example dual Primary Connector implementation is shown in Figure 95.
 
3152 This section provides the pin assignments for the Scan Chain interface signals on the Primary Connector OCP Bay. The scan chain is a point-to-point bus on a per OCP slot basis. The scan chain consists of two unidirectional busses, a common clock and a common load signal. The DATA_OUT signal serially shifts control signals from the baseboard to the OCP NIC 3.0 card. The DATA_IN signal serially shifts bits from the OCP NIC 3.0 card to the baseboard. The DATA_OUT and DATA_IN chains are independent of each other. The scan chain CLK is driven from the baseboard. The LD pin, when asserted by the baseboard, allows loading of the data on to the shift registers. An example timing diagram is shown in Figure 87. An example connection diagram is shown in Figure 89. <> 3249 This section provides the pin assignments for the Scan Chain interface signals on the Primary Connector OCP Bay. The scan chain is a point-to-point bus on a per OCP slot basis. The scan chain consists of two unidirectional busses, a common clock and a common load signal. The DATA_OUT signal serially shifts control signals from the baseboard to the OCP NIC 3.0 card. The DATA_IN signal serially shifts bits from the OCP NIC 3.0 card to the baseboard. The DATA_OUT and DATA_IN chains are independent of each other. The scan chain CLK is driven from the baseboard. The LD pin, when asserted by the baseboard, allows loading of the data on to the shift registers. An example timing diagram is shown in Figure 96. An example connection diagram is shown in Figure 98.
 
3164 For NIC implementations, the CLK pin shall be connected to Shift Registers 0 & 1, and optionally connected to Shift Registers 2 & 3 (if implemented) as defined in the text and Figure 89, below. The CLK pin shall be pulled up to +3.3V_EDGE through a 1 kΩ resistor. <> 3261 For NIC implementations, the CLK pin shall be connected to Shift Registers 0 & 1, and optionally connected to Shift Registers 2 & 3 (if implemented) as defined in the text and Figure 98, below. The CLK pin shall be pulled up to +3.3V_EDGE through a 1 kΩ resistor.
 
3176 For NIC implementations, the DATA_IN scan chain is required. The DATA_IN pin shall be connected to Shift Register 0, as defined in the text and Figure 89. <> 3273 For NIC implementations, the DATA_IN scan chain is required. The DATA_IN pin shall be connected to Shift Register 0, as defined in the text and Figure 98.
 
3182 For NIC implementations, the LD# pin implementation is required. The LD# pin shall be connected to Shift Registers 0 & 1, and optionally connected to Shift Registers 2 & 3 (if implemented) as defined in the text and Figure 89. The LD# pin shall be pulled up to +3.3V_EDGE through a 10 kΩ resistor. <> 3279 For NIC implementations, the LD# pin implementation is required. The LD# pin shall be connected to Shift Registers 0 & 1, and optionally connected to Shift Registers 2 & 3 (if implemented) as defined in the text and Figure 98. The LD# pin shall be pulled up to +3.3V_EDGE through a 10 kΩ resistor.
3183 Two possible examples for the Scan Chain timing diagram are shown in Figure 87 and Figure 88. The specific timing parameters guaranteed by the Baseboard are shown in Table 28 and timing parameters guaranteed by the OCP NIC 3.0 card are shown in Table 29. The parameters assume operation with a 15 pF load between 0 °C and 85 °C. The values are relaxed when compared to the 74LV165 datasheet and allows system implementers to use alternate implementations (such as a CPLD) instead of discrete logic parts. If the waveform in Figure 87 is implemented, the first DATA_IN bit (bit 7 on Byte 0) shall be sampled before the first rising edge of the clock that follows LD# signal rising edge. If the waveform in Figure 88 is implemented, the first DATA_IN bit shall be latched by the baseboard on the falling edge of the clock. For both examples, each subsequent DATA_IN bit shall be latched by the baseboard on the falling edge of the clock. DATA_OUT shall be driven by the baseboard such that that sufficient setup/hold time is assured to the OCP NIC 3.0 card. Note that the first bit that is shifted on DATA_IN is 0.7 (bit 7 on the least significant Byte) while the first bit that is shifted on DATA_OUT is 3.7 (bit 7 on the most significant Byte).   3280 Two possible examples for the Scan Chain timing diagram are shown in Figure 96 and Figure 97. The specific timing parameters guaranteed by the Baseboard are shown in Table 28 and timing parameters guaranteed by the OCP NIC 3.0 card are shown in Table 29. The parameters assume operation with a 15 pF load between 0 °C and 85 °C. The values are relaxed when compared to the 74LV165 datasheet and allows system implementers to use alternate implementations (such as a CPLD) instead of discrete logic parts. If the waveform in Figure 96 is implemented, the first DATA_IN bit (bit 7 on Byte 0) shall be sampled before the first rising edge of the clock that follows LD# signal rising edge. If the waveform in Figure 97 is implemented, the first DATA_IN bit shall be latched by the baseboard on the falling edge of the clock. For both examples, each subsequent DATA_IN bit shall be latched by the baseboard on the falling edge of the clock. DATA_OUT shall be driven by the baseboard such that that sufficient setup/hold time is assured to the OCP NIC 3.0 card. Note that the first bit that is shifted on DATA_IN is 0.7 (bit 7 on the least significant Byte) while the first bit that is shifted on DATA_OUT is 3.7 (bit 7 on the most significant Byte).
3184 Figure 87: Scan Chain Timing Diagram Example 1   3281 Figure 96: Scan Chain Timing Diagram Example 1
3185 Figure 88: Scan Chain Timing Diagram Example 2   3282 Figure 97: Scan Chain Timing Diagram Example 2
 
3284 For LFF designs, this bit shall also serve as the PRSNTB[0]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 89 for details. <> 3381 For LFF designs, this bit shall also serve as the PRSNTB[0]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 98 for details.
 
3292 For LFF designs, this bit shall also serve as the PRSNTB[1]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 89 for details. <> 3389 For LFF designs, this bit shall also serve as the PRSNTB[1]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 98 for details.
 
3300 For LFF designs, this bit shall also serve as the PRSNTB[2]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 89 for details. <> 3397 For LFF designs, this bit shall also serve as the PRSNTB[2]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 98 for details.
 
3312 For LFF designs, this bit shall also serve as the PRSNTB[3]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 89 for details. <> 3409 For LFF designs, this bit shall also serve as the PRSNTB[3]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 98 for details.
 
3423 Figure 89: Scan Chain Connection Example <> 3520 Figure 98: Scan Chain Connection Example
 
3426 This section provides the pin assignments for the power supply interface signals. The AC/DC specifications are defined in the PCIe CEM Specification, Rev 4.0 and amended in Section 3.9. An example connection diagram is shown in Figure 90. <> 3523 This section provides the pin assignments for the power supply interface signals. The AC/DC specifications are defined in the PCIe CEM Specification, Rev 4.0 and amended in Section 3.9. An example connection diagram is shown in Figure 99.
 
3453 AUX_PWR_EN is pinned out on both the Primary and Secondary Connector. For SFF and LFF OCP NIC 3.0 cards, the AUX_PWR_EN connection shall be implemented on the Primary Connector only. The AUX_PWR_EN connection on the Secondary Connector is reserved for a future use case. <> 3550 AUX_PWR_EN is pinned out on both the Primary and Secondary Connector. For SFF, TSFF and LFF OCP NIC 3.0 cards, the AUX_PWR_EN connection shall be implemented on the Primary Connector only. The AUX_PWR_EN connection on the Secondary Connector is reserved for a future use case.
 
3458 For OCP NIC 3.0 cards that support the Programming Mode power state, the condition AUX_PWR_EN==0 and MAIN_PWR_EN==1 shall prevent the aux power supplies from being enabled. An example of this logic is shown in Figure 90. <> 3555 For OCP NIC 3.0 cards that support the Programming Mode power state, the condition AUX_PWR_EN==0 and MAIN_PWR_EN==1 shall prevent the aux power supplies from being enabled. An example of this logic is shown in Figure 99.
 
3466 For OCP NIC 3.0 cards that support the Programming Mode power state, the condition AUX_PWR_EN == 0 and MAIN_PWR_EN == 1 shall prevent the main power supplies from being enabled. An example of this gating logic is shown in Figure 90. <> 3563 For OCP NIC 3.0 cards that support the Programming Mode power state, the condition AUX_PWR_EN == 0 and MAIN_PWR_EN == 1 shall prevent the main power supplies from being enabled. An example of this gating logic is shown in Figure 99.
 
3512 Refer to the power up and power down sequencing diagrams (Figure 107 and Figure 108) for timing details. <> 3609 Refer to the power up and power down sequencing diagrams (Figure 116 and Figure 117) for timing details.
3513 Where appropriate, designs that have a separate Main Power domain should also connect to the main power good indication to the NIC_PWR_GOOD signal via a FET to isolate the domains. Refer to Figure 90 for an example implementation.   3610 Where appropriate, designs that have a separate Main Power domain should also connect to the main power good indication to the NIC_PWR_GOOD signal via a FET to isolate the domains. Refer to Figure 99 for an example implementation.
 
3519 Figure 90: Example Power Supply Topology <> 3616 Figure 99: Example Power Supply Topology
 
3521 This section provides the pin assignments for the USB 2.0 interface signals. USB 2.0 is only defined for operation on the Primary Connector. USB 2.0 may be used for applications with end point silicon that requires a USB connection to the baseboard. Implementations may also allow for a USB-Serial or USB-JTAG translator for serial or JTAG applications. If multiple USB devices are required, an optional USB hub may be implemented on the OCP NIC 3.0 card. Downstream device discovery is completed as part of the bus enumeration per the USB 2.0 specification. A basic example connection diagram is shown in Figure 91. An example depicting USB-Serial and USB-JTAG connectivity with an USB hub is shown in Figure 92. <> 3618 This section provides the pin assignments for the USB 2.0 interface signals. USB 2.0 is only defined for operation on the Primary Connector. USB 2.0 may be used for applications with end point silicon that requires a USB connection to the baseboard. Implementations may also allow for a USB-Serial or USB-JTAG translator for serial or JTAG applications. If multiple USB devices are required, an optional USB hub may be implemented on the OCP NIC 3.0 card. Downstream device discovery is completed as part of the bus enumeration per the USB 2.0 specification. A basic example connection diagram is shown in Figure 100. An example depicting USB-Serial and USB-JTAG connectivity with an USB hub is shown in Figure 101.
 
3539 Figure 91: USB 2.0 Connection Example – Basic Connectivity <> 3636 Figure 100: USB 2.0 Connection Example – Basic Connectivity
3540 Figure 92: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity   3637 Figure 101: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity
 
3542 This section provides the pin assignments for the UART interface signals. UART is only defined for operation on the Secondary Connector. The UART pins may be used with end point silicon that require console redirection over the baseboard – such as LFF SmartNICs. An example connection diagram is shown in Figure 93. <> 3639 This section provides the pin assignments for the UART interface signals. UART is only defined for operation on the Secondary Connector. The UART pins may be used with end point silicon that require console redirection over the baseboard – such as LFF SmartNICs. An example connection diagram is shown in Figure 102.
 
3562 Figure 93: UART Connection Example <> 3659 Figure 102: UART Connection Example
 
3574 In this release of the OCP NIC 3.0 specification, the RFU[1:2] pins are defined on the Primary Connector. RFU[3:4] are defined on the Secondary Connector. A total of two reserved pins are available for the SFF; a total of four reserved pins are available for the LFF. <> 3671 In this release of the OCP NIC 3.0 specification, the RFU[1:2] pins are defined on the Primary Connector. RFU[3:4] are defined on the Secondary Connector. A total of two reserved pins are available for the SFF and TSFF; a total of four reserved pins are available for the LFF.
 
3579 PRSNTA#, PRSNTB[3:0]#. The PRSNTA# pin shall connect to the PRSNTB# pins as a hard coded value on the OCP NIC 3.0 card. The encoding of the PRSNTB[3:0]# pins allows the baseboard to determine the PCIe Links available on the OCP NIC 3.0 card. PRSNTA# and PRSNTB[3:0]# pins exist for each connector. For the SFF, a baseboard shall read the pins associated with the Primary Connector to determine the card type. For the LFF, a baseboard shall read the pins associated with both the Primary and Secondary Connector to determine the card type. <> 3676 PRSNTA#, PRSNTB[3:0]#. The PRSNTA# pin shall connect to the PRSNTB# pins as a hard coded value on the OCP NIC 3.0 card. The encoding of the PRSNTB[3:0]# pins allows the baseboard to determine the PCIe Links available on the OCP NIC 3.0 card. PRSNTA# and PRSNTB[3:0]# pins exist for each connector. For the SFF and TSFF, a baseboard shall read the pins associated with the Primary Connector to determine the card type. For the LFF, a baseboard shall read the pins associated with both the Primary and Secondary Connector to determine the card type.
 
3581 A high level bifurcation connection diagram is shown in Figure 82. <> 3678 A high-level bifurcation connection diagram is shown in Figure 91.
 
3583 The OCP NIC 3.0 card to baseboard configuration mechanism consists of four dual use pins (PRSNTB[3:0]#) on the OCP NIC 3.0 card and a grounded PRSNTA# pin on the baseboard per connector. For the SFF, a baseboard shall read the pins associated with the Primary Connector to determine the card type. For the LFF, a baseboard shall read the pins associated with both the Primary and Secondary Connector to determine the card type. These pins provide card presence detection as well as mechanism to notify the baseboard of the pre-defined PCIe lane width capabilities. The PRSNTB[3:0]# pins are pulled up to +3.3V_EDGE on the baseboard and are active low signals. A state of 0b1111 indicates that no card is present in the connector(s). Depending on the capabilities of the OCP NIC 3.0 card, a selection of PRSNTB[3:0]# signals may be strapped to the PRSNTA# signal and is pulled low by the baseboard. The encoding of the PRSTNB[3:0]# bits is shown in Table 36 for x32, x16 and x8 PCIe cards. While SFF and LFF cards are allowed in an LFF compliant slot, the condition where the Primary Connector PRSNTB[3:0]# equals 0b1111 and the Secondary Connector PRSNTB[3:0]# pins is not equal to 0b1111 is invalid. <> 3680 The OCP NIC 3.0 card to baseboard configuration mechanism consists of four dual use pins (PRSNTB[3:0]#) on the OCP NIC 3.0 card and a grounded PRSNTA# pin on the baseboard per connector. For the SFF and TSFF, a baseboard shall read the pins associated with the Primary Connector to determine the card type. For the LFF, a baseboard shall read the pins associated with both the Primary and Secondary Connector to determine the card type. These pins provide card presence detection as well as mechanism to notify the baseboard of the pre-defined PCIe lane width capabilities. The PRSNTB[3:0]# pins are pulled up to +3.3V_EDGE on the baseboard and are active low signals. A state of 0b1111 indicates that no card is present in the connector(s). Depending on the capabilities of the OCP NIC 3.0 card, a selection of PRSNTB[3:0]# signals may be strapped to the PRSNTA# signal and is pulled low by the baseboard. The encoding of the PRSTNB[3:0]# bits is shown in Table 36 for x32, x16 and x8 PCIe cards. While SFF and LFF cards are allowed in an LFF compliant slot, the condition where the Primary Connector PRSNTB[3:0]# equals 0b1111 and the Secondary Connector PRSNTB[3:0]# pins is not equal to 0b1111 is invalid.
 
3585 Three signals (BIF[2:0]#) are driven by the baseboard to notify requested bifurcation on the OCP NIC 3.0 card silicon. This allows the baseboard to set the lane configuration on the OCP NIC 3.0 card that supports multiple bifurcation options. BIF[2:0]# pins exist on each connector. For the SFF, the BIF[2:0]# pins associated with the Primary Connector are used. For the LFF, the BIF[2:0]# pins associated with both the Primary and Secondary Connector are used to determine the requested bifurcation.  <> 3682 Three signals (BIF[2:0]#) are driven by the baseboard to notify requested bifurcation on the OCP NIC 3.0 card silicon. This allows the baseboard to set the lane configuration on the OCP NIC 3.0 card that supports multiple bifurcation options. BIF[2:0]# pins exist on each connector. For the SFF and TSFF, the BIF[2:0]# pins associated with the Primary Connector are used. For the LFF, the BIF[2:0]# pins associated with both the Primary and Secondary Connector are used to determine the requested bifurcation. 
3586 For example, a baseboard that has four separate hosts that support a 4 x4 connection, should appropriately drive the BIF[2:0]# pins per Table 36 and indicate to the SFF OCP NIC 3.0 card silicon to setup a 4 x4 configuration.   3683 For example, a baseboard that has four separate hosts that support a 4 x4 connection, should appropriately drive the BIF[2:0]# pins per Table 36 and indicate to the SFF/TSFF OCP NIC 3.0 card silicon to setup a 4 x4 configuration.
 
3601 The BIF[2:0]# pins must be in their valid states upon the assertion of AUX_PWR_EN. <> 3698 The BIF[2:0]# pins must be in their valid states upon the assertion of AUX_PWR_EN. The BIF[2:0]# pins shall remain static after AUX_PWR_EN is asserted. The pins are not allowed to change states when the OCP NIC 3.0 card is powered on.
 
3605 PERST# shall be deasserted >1 s after NIC_PWR_GOOD assertion as defined in Figure 107. Refer to Section 3.11 for timing details. <> 3702 PERST# shall be deasserted >1 s after NIC_PWR_GOOD assertion as defined in Figure 116. Refer to Section 3.11 for timing details.
 
3609 Figure 94 illustrates a single host baseboard that supports x16 with a single controller OCP NIC 3.0 card that also supports x16. The PRSTNB[3:0]# state is 0b0111. The BIF[2:0]# state is 0b000 to set the card as a 1x16 for bifurcation capable controllers. For controllers without bifurcation support, the BIF[2:0] pin connections are not required on the card. The PRSNTB encoding notifies the baseboard that this card is only capable of 1 x16. The single host baseboard determines that it is also capable of supporting 1 x16. The resulting link width is 1 x16. <> 3706 Figure 103 illustrates a single host baseboard that supports x16 with a single controller OCP NIC 3.0 card that also supports x16. The PRSTNB[3:0]# state is 0b0111. The BIF[2:0]# state is 0b000 to set the card as a 1x16 for bifurcation capable controllers. For controllers without bifurcation support, the BIF[2:0] pin connections are not required on the card. The PRSNTB encoding notifies the baseboard that this card is only capable of 1 x16. The single host baseboard determines that it is also capable of supporting 1 x16. The resulting link width is 1 x16.
3610 Figure 94: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller)   3707 Figure 103: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller)
 
3613 Figure 95 illustrates a single host baseboard that supports 2 x8 with a dual controller OCP NIC 3.0 card that also supports 2 x8. The PRSTNB[3:0]# state is 0b0110. The BIF[2:0]# state is 0b000 in this example because the network card only supports a 2x8. The PRSNTB encoding notifies the baseboard that this card is only capable of 2 x8. The single host baseboard determines that it is also capable of supporting 2 x8. The resulting link width is 2 x8. <> 3710 Figure 104 illustrates a single host baseboard that supports 2 x8 with a dual controller OCP NIC 3.0 card that also supports 2 x8. The PRSTNB[3:0]# state is 0b0110. The BIF[2:0]# state is 0b000 in this example because the network card only supports a 2x8. The PRSNTB encoding notifies the baseboard that this card is only capable of 2 x8. The single host baseboard determines that it is also capable of supporting 2 x8. The resulting link width is 2 x8.
3614 Figure 95: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)   3711 Figure 104: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)
 
3616 Figure 96 illustrates a quad host baseboard that supports 4 x4 with a single controller OCP NIC 3.0 card that supports 1 x16, 2 x8 and 4 x4. The PRSTNB[3:0]# state is 0b0100. The BIF[2:0]# state in this example is 0b110 as the end point network controller is forced to bifurcate to 4 x4. The PRSNTB encoding notifies the baseboard that this card is only capable of 1 x16, 2 x8 and 4 x4. The quad host baseboard determines that it is also capable of supporting 4 x4. The resulting link width is 4 x4. <> 3713 Figure 105 illustrates a quad host baseboard that supports 4 x4 with a single controller OCP NIC 3.0 card that supports 1 x16, 2 x8 and 4 x4. The PRSTNB[3:0]# state is 0b0100. The BIF[2:0]# state in this example is 0b110 as the end point network controller is forced to bifurcate to 4 x4. The PRSNTB encoding notifies the baseboard that this card is only capable of 1 x16, 2 x8 and 4 x4. The quad host baseboard determines that it is also capable of supporting 4 x4. The resulting link width is 4 x4.
3617 Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller)   3714 Figure 105: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller)
 
3619 Figure 97 illustrates a quad host baseboard that supports 4 x4 with a quad controller OCP NIC 3.0 card that supports 4 x4. The PRSTNB[3:0]# state is 0b0011. The BIF[2:0]# state is a don’t care value as there is no need to instruct the end-point network controllers to a specific bifurcation (each controller only supports 1x4 in this example). The PRSNTB encoding notifies the baseboard that this card is only capable of 4 x4. The quad host baseboard determines that it is also capable of supporting 4 x4. The resulting link width is 4 x4. <> 3716 Figure 106 illustrates a quad host baseboard that supports 4 x4 with a quad controller OCP NIC 3.0 card that supports 4 x4. The PRSTNB[3:0]# state is 0b0011. The BIF[2:0]# state is a don’t care value as there is no need to instruct the end-point network controllers to a specific bifurcation (each controller only supports 1x4 in this example). The PRSNTB encoding notifies the baseboard that this card is only capable of 4 x4. The quad host baseboard determines that it is also capable of supporting 4 x4. The resulting link width is 4 x4.
3620 Figure 97: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers)   3717 Figure 106: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers)
 
3622 Figure 98 illustrates a single host baseboard that supports 1 x16 with a dual controller OCP NIC 3.0 card that supports 2 x8. The PRSTNB[3:0]# state is 0b0110. The BIF[2:0]# state is 0b000 as each silicon instance only supports 1x8. The PRSNTB encoding notifies the baseboard that this card is only capable of 2 x8. The quad host baseboard determines that it is capable of 1x 16, but down shifts to 1 x8. The resulting link width is 1 x8 and only on endpoint 0. <> 3719 Figure 107 illustrates a single host baseboard that supports 1 x16 with a dual controller OCP NIC 3.0 card that supports 2 x8. The PRSTNB[3:0]# state is 0b0110. The BIF[2:0]# state is 0b000 as each silicon instance only supports 1x8. The PRSNTB encoding notifies the baseboard that this card is only capable of 2 x8. The quad host baseboard determines that it is capable of 1x 16, but down shifts to 1 x8. The resulting link width is 1 x8 and only on endpoint 0.
3623 Figure 98: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)   3720 Figure 107: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)
 
3626 REFCLK[0:3] and PERST[0:3]# are defined for use in this release of the specification. REFCLK[4:5] and PERST[4:5]# are not currently defined for use. The following tables enumerate the REFCLK and PERST# mapping for SFF cards for 1, 2 and 4 links; LFF cards for 1, 2, 4 and 8 links. For a LFF 8 link scenario, the lower x4 “link-a” and upper x4 “link-b” of each x8 lanes are expected to use the same REFCLK and PERST (see Table 39). A 1:2 clock driver circuit is expected on the OCP NIC 3.0 card in this case. <> 3723 REFCLK[0:3] and PERST[0:3]# are defined for use in this release of the specification. REFCLK[4:5] and PERST[4:5]# are not currently defined for use. The following tables enumerate the REFCLK and PERST# mapping for SFF and TSFF cards for 1, 2 and 4 links; LFF cards for 1, 2, 4 and 8 links. For a LFF 8 link scenario, the lower x4 “link-a” and upper x4 “link-b” of each x8 lanes are expected to use the same REFCLK and PERST (see Table 39). A 1:2 clock driver circuit is expected on the OCP NIC 3.0 card in this case.
 
3657 Table 38: SFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links <> 3754 Table 38: SFF, TSFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links
 
3696 SFF PCIe REFCLK and PERST# Mapping <> 3793 SFF, TSFF PCIe REFCLK and PERST# Mapping
3697 The following figures show the Link n, REFCLKn, PERSTn mapping for the SFF with 1, 2 and 4 links as single, dual and quad host configurations. For clarity, the PCIe sideband signals are not illustrated in this section. Please refer to the signal descriptions and associated diagrams for connectivity requirements.   3794 The following figures show the Link n, REFCLKn, PERSTn mapping for the SFF/TSFF with 1, 2 and 4 links as single, dual and quad host configurations. For clarity, the PCIe sideband signals are not illustrated in this section. Please refer to the signal descriptions and associated diagrams for connectivity requirements.
3698 Figure 99: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links   3795 Figure 108: SFF/TSFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links
3699 Figure 100: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links   3796 Figure 109: SFF/TSFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links
3700 Note: For dual host applications that connect to a two link endpoint, the baseboard Host 1 REFCLK0 and PERST0 signal needs to be multiplexed to the REFCLK1 and PERST1 pins of the OCP NIC 3.0 card edge. This ensures the mandated Link n, REFCLKn and PERSTn mappings are maintained.   3797 Note: For dual host applications that connect to a two-link endpoint, the baseboard Host 1 REFCLK0 and PERST0 signal needs to be multiplexed to the REFCLK1 and PERST1 pins of the OCP NIC 3.0 card edge. This ensures the mandated Link n, REFCLKn and PERSTn mappings are maintained.
3701 Figure 101: SFF PCIe REFCLK Mapping – Quad Host – 4 Links   3798 Figure 110: SFF/TSFF PCIe REFCLK Mapping – Quad Host – 4 Links
 
3705 Figure 102: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links <> 3802 Figure 111: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links
3706 Figure 103: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links   3803 Figure 112: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links
 
3708 Figure 104: LFF PCIe REFCLK Mapping – Quad Host – 4 Links <> 3805 Figure 113: LFF PCIe REFCLK Mapping – Quad Host – 4 Links
 
3718 The numbering of all OCP NIC 3.0 external ports shall start from Port 1. When oriented with the primary side components facing up and viewing directly into the port, Port 1 shall be located on the left hand side. The port numbers shall sequentially increase to the right. Refer to Figure 105 as an example implementation. <> 3815 The numbering of all OCP NIC 3.0 external ports shall start from Port 1. When oriented with the primary side components facing up and viewing directly into the port, Port 1 shall be located on the left-hand side. The port numbers shall sequentially increase to the right. Refer to Figure 114 as an example implementation.
 
3720 For low I/O count SFF cards without built in light pipes (such as 1x QSFP, 2x QSFP, 2x SFP, or 2x RJ45), or LFF cards, where additional I/O bracket area is available, the card shall locally implement on-board link/activity indications. The card may additionally implement LEDs on the optional Scan Chain data stream. <> 3817 For low I/O count SFF/TSFF cards without built in light pipes (such as 1x QSFP, 2x QSFP, 2x SFP, or 2x RJ45), or LFF cards, where additional I/O bracket area is available, the card shall locally implement on-board link/activity indications. The card may additionally implement LEDs on the optional Scan Chain data stream.
 
3770 Figure 105: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement <> 3867 Figure 114: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement
 
3772 Note 1: The example port and LED ordering diagrams shown in Figure 105 are viewed with the card in the horizontal position and the primary side is facing up. <> 3869 Note 1: The example port and LED ordering diagrams shown in Figure 114 are viewed with the card in the horizontal position and the primary side is facing up.
 
    -+ 3871 Note 3: For TSFF, there may be sufficient space to place LEDs above the port depending on the I/O configuration. Light pipes may be used in this configuration at the discretion of the OCP NIC 3.0 card designer.
 
3781 There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode, and Main Power Mode. These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 106 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.11. <> 3879 There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode, and Main Power Mode. These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 115 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.11.
3782 Figure 106: Baseboard Power States   3880 Figure 115: Baseboard Power States
 
3845 Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in ID Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max voltage leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 300 mV when a 1 kΩ bleed resistor is present on the baseboard. The baseboard bleed resistor is optional if the baseboard can tolerate leakage. If +12V_EDGE is present in ID Mode, the max current is defined in Section 3.9. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0. <> 3942 Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in ID Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max voltage leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 300 mV when a 1 kΩ bleed resistor is present on the baseboard. The baseboard bleed resistor is optional if the baseboard can tolerate leakage. If +12V_EDGE is present in ID Mode, the max current is defined in Section 3.9.
 
3847 The Aux Power Mode provides both +3.3V_EDGE as well as +12V_EDGE is available. +12V_EDGE in Aux mode may be used to deliver power to the OCP NIC 3.0 card, but only up to the Aux mode budget as defined in Table 42. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=0, NIC_PWR_GOOD=1 and the duration (TAPL) has passed for the ID-Aux Power Mode ramp. This guarantees the ID mode to Aux Power Mode transition (as shown in Figure 107) has completed and all Aux Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met. <> 3944 The Aux Power Mode provides both +3.3V_EDGE as well as +12V_EDGE is available. +12V_EDGE in Aux mode may be used to deliver power to the OCP NIC 3.0 card, but only up to the Aux mode budget as defined in Table 42. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=0, NIC_PWR_GOOD=1 and the duration (TAPL) has passed for the ID-Aux Power Mode ramp. This guarantees the ID mode to Aux Power Mode transition (as shown in Figure 116) has completed and all Aux Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not be sampled until these conditions are met.
 
3850 The Main Power Mode provides both +3.3V_EDGE and +12V_EDGE across the OCP connector. The OCP NIC 3.0 card operates in full capacity. Up to 80 W may be delivered on +12V_EDGE for a SFF Card and up to 150 W for a LFF Card. Additionally, up to 3.63 W is delivered on each +3.3V_EDGE pin. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=1, NIC_PWR_GOOD=1 and the duration (TMPL) has passed for the Aux-Main Power Mode ramp. This guarantees the Aux Power Mode to Main Power Mode transition (as shown in Figure 107) has completed and all Main Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met. <> 3947 The Main Power Mode provides both +3.3V_EDGE and +12V_EDGE across the OCP connector. The OCP NIC 3.0 card operates in full capacity. Up to 80 W may be delivered on +12V_EDGE for a SFF/TSFF Card and up to 150 W for a LFF Card. Additionally, up to 3.63 W is delivered on each +3.3V_EDGE pin. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=1, NIC_PWR_GOOD=1 and the duration (TMPL) has passed for the Aux-Main Power Mode ramp. This guarantees the Aux Power Mode to Main Power Mode transition (as shown in Figure 116) has completed and all Main Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not be sampled until these conditions are met.
 
3855 Additionally, the Aux Power Mode and Main Power Mode SVRs need to remain disabled and NIC_PWR_GOOD shall remain low while the card is in this state. An example discrete logic circuit to accomplish this gating is shown in Figure 90. NIC vendors may implement their own gating circuitry if the same result is achieved. <> 3952 Additionally, the Aux Power Mode and Main Power Mode SVRs need to remain disabled and NIC_PWR_GOOD shall remain low while the card is in this state. An example discrete logic circuit to accomplish this gating is shown in Figure 99. NIC vendors may implement their own gating circuitry if the same result is achieved.
 
3858 The baseboard provides +3.3V_EDGE and +12V_EDGE to both the Primary and Secondary Connectors. The rail requirements are leveraged from the PCIe CEM 4.0 specification. For OCP NIC 3.0 implementations, there are six total power envelopes. Five are defined for SFF, and one is defined for LFF. The max current draw is defined in Table 42 for each state and power envelope and is inclusive of the line side transceivers installed on the card. The slot power values are the max supportable power delivered to the card for each slot type. This is independent of the +3.3V_EDGE and +12V_EDGE rails deviating from their nominal values. <> 3955 The baseboard provides +3.3V_EDGE and +12V_EDGE to both the Primary and Secondary Connectors. The rail requirements are leveraged from the PCIe CEM 4.0 specification. For OCP NIC 3.0 implementations, there are six total power envelopes. Five are defined for SFF/TSFF, and one is defined for LFF. The max current draw is defined in Table 42 for each state and power envelope and is inclusive of the line side transceivers installed on the card. The slot power values are the max supportable power delivered to the card for each slot type. This is independent of the +3.3V_EDGE and +12V_EDGE rails deviating from their nominal values.
 
3861 15 W SlotSFF <> 3958 15 W SlotSFF/TSFF
 
3863 SFF <> 3960 SFF/TSFF
3864 35 W Slot SFF   3961 35 W Slot SFF/TSFF
3865 50 W Slot SFF   3962 50 W Slot SFF/TSFF
3866 80 W Slot SFF   3963 80 W Slot SFF/TSFF
 
3957 The OCP NIC 3.0 FRU definition provides a record for the max power consumption of the card. This value shall be used to aid in determining if the card may be enabled in a given OCP slot. Refer to Section 4.10.3 for the available FRU records. <> 4054 The OCP NIC 3.0 FRU definition provides a record for the max power consumption of the card. This value shall be used to aid in determining if the card may be enabled for a given OCP slot. Refer to Section 4.10.3 for the available FRU records.
 
3968 Figure 107: Power-Up Sequencing – Normal Operation <> 4065 Figure 116: Power-Up Sequencing – Normal Operation
 
3970 Figure 108: Power-Down Sequencing – Normal Operation <> 4067 Figure 117: Power-Down Sequencing – Normal Operation
 
3972 Figure 109: Programming Mode Sequencing <> 4069 Figure 118: Programming Mode Sequencing
 
4024 Minimum time between AUX_PWR_EN deassertion to AUX_PWR_EN reassertion for SFF cards. Delay time allows for OCP NIC 3.0 card capacitors to discharge and prevent reapplying power into a pre-biased condition. <> 4121 Minimum time between AUX_PWR_EN deassertion to AUX_PWR_EN reassertion for SFF/TSFF cards. Delay time allows for OCP NIC 3.0 card capacitors to discharge and prevent reapplying power into a pre-biased condition.
 
4245 If the self-shutdown feature is implemented, the NIC ASIC shall monitor its temperature and shut-down itself as soon as the self-shutdown threshold value is reached. The value of the self-shutdown threshold is implementation specific. It is recommended that the self-shutdown threshold value is higher than the maximum junction temperature of the ASIC implementing the NIC function. It is also recommended that the self-shutdown threshold value is between the critical and fatal temperature thresholds of the ASIC. <> 4342 If the self-shutdown feature is implemented, the NIC ASIC shall monitor its temperature and shutdown itself as soon as the self-shutdown threshold value is reached. The value of the self-shutdown threshold is implementation specific. It is recommended that the self-shutdown threshold value is higher than the maximum junction temperature of the ASIC implementing the NIC function. It is also recommended that the self-shutdown threshold value is above the fatal temperature threshold of the ASIC. This allows the fatal temperature threshold crossing to be logged and for the BMC to take action (e.g. a controlled shutdown) while remaining as a failsafe for systems without alert support.
 
4376 For baseboards that implement two or more Primary Connectors, the NC-SI over RBT arbitration ring shall be connected to each other. The arbitration ring shall support operation with one card, or multiple cards installed. Figure 86 shows an example connection with dual Primary Connectors. <> 4473 For baseboards that implement two or more Primary Connectors, the NC-SI over RBT arbitration ring shall be connected to each other. The arbitration ring shall support operation with one card, or multiple cards installed. Figure 95 shows an example connection with dual Primary Connectors.
 
4435 The permissible EEPROM addresses are indicated in Table 56. The write/read pair is presented in 8-bit format. The EEPROM shall use double byte addressing and, at minimum, shall be of sufficient size to hold the base FRU contents and any vendor specific information. The double byte write and read accesses are shown in 110 and Figure 111. Refer to the I2C specification for timing details. <> 4532 The permissible EEPROM addresses are indicated in Table 56. The write/read pair is presented in 8-bit format. The EEPROM shall use double byte addressing and, at minimum, shall be of sufficient size to hold the base FRU contents and any vendor specific information. The double byte write and read accesses are shown in 119 and Figure 120. Refer to the I2C specification for timing details.
4436 Figure 110: FRU EEPROM Writes with Double Byte Addressing   4533 Figure 119: FRU EEPROM Writes with Double Byte Addressing
4437 Figure 111: FRU EEPROM Reads with Double Byte Addressing   4534 Figure 120: FRU EEPROM Reads with Double Byte Addressing
 
4440 The FRU update flow is shown in Figure 112. <> 4537 The FRU update flow is shown in Figure 121.
4441 Figure 112: FRU Update Flow   4538 Figure 121: FRU Update Flow
 
4458 0x00 – Reserved0x01 – OCP NIC 3.0 card FRU record released with version 0.90 <> 4555 0x00 – Reserved0x01 – OCP NIC 3.0 card FRU record released with version 0.900x02 – OCP NIC 3.0 card FRU record released with version 1.10x03 – OCP NIC 3.0 card FRU record released with version 1.20x04 – 0xFF – Reserved
4459 0x02 – OCP NIC 3.0 card FRU record released with version 1.10x03 – 0xFF – Reserved      
 
4574 29:30 <> 4670 29
4575 2   4671 1
      4672 Self-shutdown Temperature.
      4673 This byte represents the temperature threshold at which the optional self-shutdown will occur. Temperature values are represented in degrees Celsius and is encoded in hexadecimal. This value is recommended to be above the upper fatal threshold of the NIC. If self-shutdown is not used, this value shall be set to 0xFF.
      4674 0x00-0xFE – Temperature at which self-shutdown occurs.0xFF – Self-shutdown is not implemented.
      4675 30
      4676 1
 
4577 Set each byte to 0xFF for this version of the specification. <> 4678 Set the byte to 0xFF for this version of the specification.
 
4609 The NC-SI over RBT requirements in this section apply to both the SFF and LFF OCP NIC 3.0 cards. Designers shall use the appropriate SFF or LFF timing parameters for the design calculations. <> 4710 The NC-SI over RBT requirements in this section apply to the SFF, TSFF and LFF OCP NIC 3.0 cards. Designers shall use the appropriate SFF, TSFF or LFF timing parameters for the design calculations. The SFF and TSFF timing parameters are equivalent since the same card and baseboard PBA may be used.
 
4624 Max permissible propagation delay on a SFF baseboard. <> 4725 Max permissible propagation delay on a SFF/TSFF baseboard.
 
4630 Max permissible propagation delay for a SFF OCP NIC 3.0 card. <> 4731 Max permissible propagation delay for a SFF/TSFF OCP NIC 3.0 card.
 
4664 Figure 113: NC-SI over RBT Timing Budget Topology <> 4765 Figure 122: NC-SI over RBT Timing Budget Topology
 
4667 SFF Baseboard Requirements <> 4768 SFF/TSFF Baseboard Requirements
4668 The SFF baseboard is allocated a maximum propagation time of 2100 ps between the BMC and the connector edge. NC-SI over RBT isolation buffers are required on the baseboard. The requirements for additional add-in card loading are reduced. The available timing budget for the SFF baseboard is computed by the formula below.   4769 The SFF/TSFF baseboard is allocated a maximum propagation time of 2100 ps between the BMC and the connector edge. NC-SI over RBT isolation buffers are required on the baseboard. The requirements for additional add-in card loading are reduced. The available timing budget for the SFF/TSFF baseboard is computed by the formula below.
 
4670 The skew requirement defines the max permissible clock skew (TSKEW) between any two system devices. The TSKEW calculation is computed by the formula below. This applies to both the devices on the baseboard and the NIC. L1 is the REF_CLK segment from the baseboard 50 MHz reference clock generator to the BMC. L2 is the REF_CLK segment between the baseboard clock generator to the OCP NIC 3.0 connector and L3 is the segment between the SFF OCP NIC 3.0 card gold fingers and the target ASIC. Refer to Figure 113 for details. The max permissible value of L3 is TNIC,SFF = 900 ps as discussed in Section 5.1.3. Baseboard vendors shall take this value into consideration when analyzing the available timing budget. <> 4771 The skew requirement defines the max permissible clock skew (TSKEW) between any two system devices. The TSKEW calculation is computed by the formula below. This applies to both the devices on the baseboard and the NIC. L1 is the REF_CLK segment from the baseboard 50 MHz reference clock generator to the BMC. L2 is the REF_CLK segment between the baseboard clock generator to the OCP NIC 3.0 connector and L3 is the segment between the SFF/TSFF OCP NIC 3.0 card gold fingers and the target ASIC. Refer to Figure 122 for details. The max permissible value of L3 is TNIC,SFF = 900 ps as discussed in Section 5.1.3. Baseboard vendors shall take this value into consideration when analyzing the available timing budget.
 
4675 Similar to SFF, the LFF clock skew parameter TSKEW(max) must not be exceeded. The max permissible value of L3 is TNIC,LFF = 1350 ps. Refer to Section 5.1.1 for the skew computation requirements. <> 4776 Similar to the SFF/TSFF implementation, the LFF clock skew parameter TSKEW(max) must not be exceeded. The max permissible value of L3 is TNIC,LFF = 1350 ps. Refer to Section 5.1.1 for the skew computation requirements.
4676 SFF OCP NIC 3.0 Card Requirements   4777 SFF/TSFF OCP NIC 3.0 Card Requirements
4677 The SFF OCP NIC 3.0 card is allocated a maximum propagation time of TNIC,SFF = 900 ps between the card gold finger and the ASIC pad for both the clock and data signals. The total card propagation delay from the RBT clock input towards the card to the RBT outputs from the card shall be less than 14.3 ns (TCO(max) + 2 x TNIC,SFF) when measured at the corresponding SFF OCP NIC 3.0 gold fingers. This can be achieved by using an ASIC with the worst case Clock-to-Out (TCO,MAX) value of 12.5 ns specified by DSP0222, and each SFF OCP NIC 3.0 card-side RBT signal not exceeding a max propagation time of 900 ps.   4778 The SFF/TSFF OCP NIC 3.0 card is allocated a maximum propagation time of TNIC,SFF = 900 ps between the card gold finger and the ASIC pad for both the clock and data signals. The total card propagation delay from the RBT clock input towards the card to the RBT outputs from the card shall be less than 14.3 ns (TCO(max) + 2 x TNIC,SFF) when measured at the corresponding SFF/TSFF OCP NIC 3.0 gold fingers. This can be achieved by using an ASIC with the worst case Clock-to-Out (TCO,MAX) value of 12.5 ns specified by DSP0222, and each SFF/TSFF OCP NIC 3.0 card-side RBT signal not exceeding a max propagation time of 900 ps.
4678 This propagation delay is equivalent to a max length of 5.1 inches assuming standard FR4 material with a propagation delay of 175 ps/in. Additional trace length may be achieved with the use of a higher propagation velocity material (e.g., material with a lower dielectric constant) on the baseboard and OCP NIC 3.0 card or simultaneously using both BMC and ASIC devices with an improved timing from Clock-to-Out (TCO,MAX) value compared to the published value of 12.5 ns in DSP0222. For NIC implementations with clock buffers, the propagation delay of the buffer needs to be included in this timing budget (i.e.,  L3 + TCLK_BUF + L3’ + TCO,MAX + L5 shall be less than 14.3 ns) as shown in Figure 115.   4779 This propagation delay is equivalent to a max length of 5.1 inches assuming standard FR4 material with a propagation delay of 175 ps/in. Additional trace length may be achieved with the use of a higher propagation velocity material (e.g., material with a lower dielectric constant) on the baseboard and OCP NIC 3.0 card or simultaneously using both BMC and ASIC devices with an improved timing from Clock-to-Out (TCO,MAX) value compared to the published value of 12.5 ns in DSP0222. For NIC implementations with clock buffers, the propagation delay of the buffer needs to be included in this timing budget (i.e.,  L3 + TCLK_BUF + L3’ + TCO,MAX + L5 shall be less than 14.3 ns) as shown in Figure 124.
4679 If multiple ASICs are utilized, the RBT_CLK_IN signal may be routed with a T-topology as shown in Figure 114. The trace length would be calculated as the delay summation of segment L3 + L3’ for ASIC #0 and L3 + L3” for ASIC #1.  The data path delay to the ASIC is L5.   4780 If multiple ASICs are utilized, the RBT_CLK_IN signal may be routed with a T-topology as shown in Figure 123. The trace length would be calculated as the delay summation of segment L3 + L3’ for ASIC #0 and L3 + L3” for ASIC #1.  The data path delay to the ASIC is L5.
4680 Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer   4781 Figure 123: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer
4681 A clock buffer is optionally permitted if the NIC timing budget is not violated. This is shown in Figure 115. In this case, the trace length would be calculated as the delay summation of trace segment L3 + TCLK_BUF + L3’ for ASIC #0, and L3 + TCLK_BUF + L3’ for ASIC #1.   4782 A clock buffer is optionally permitted if the NIC timing budget is not violated. This is shown in Figure 124. In this case, the trace length would be calculated as the delay summation of trace segment L3 + TCLK_BUF + L3’ for ASIC #0, and L3 + TCLK_BUF + L3’ for ASIC #1.
4682 Figure 115: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer   4783 Figure 124: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer
 
4684 Similar to the SFF, a LFF OCP NIC 3.0 Card is allocated a maximum propagation time of TNIC,LFF = 1350 ps between the card gold finger and the ASIC pad for both the clock and data signals. The segment L3 between the LFF OCP NIC 3.0 card gold fingers and the ASIC shall not exceed this propagation delay for a single and multi-ASIC target implementations. Refer to Section 5.1.3 for computation and topology considerations. <> 4785 Similar to the SFF/TSFF, a LFF OCP NIC 3.0 Card is allocated a maximum propagation time of TNIC,LFF = 1350 ps between the card gold finger and the ASIC pad for both the clock and data signals. The segment L3 between the LFF OCP NIC 3.0 card gold fingers and the ASIC shall not exceed this propagation delay for a single and multi-ASIC target implementations. Refer to Section 5.1.3 for computation and topology considerations.
 
4690 The OCP NIC 3.0 PCIe channel requirements for PCI Express® Gen 4.0 align with the electrical budget and constraints as detailed in the PCI Express® CEM 4.0 Rev 1.0 and PCI Express Base Specification Rev 4.0. Exceptions or clarifications to the referenced specifications are noted in the sections below. The OCP NIC 3.0 PCIe channel requirements for PCI Express® Gen 5.0 differ from the PCI Express® CEM 5.0 Rev 0.7 for Insertion Loss Values as the loss was reduced on the OCP NIC 3.0 to allow the baseboard additional margin for SFF implementations. The OCP NIC 3.0 LFF aligns with the specification. Refer to Section 5.3.1.2 for details. <> 4791 The OCP NIC 3.0 PCIe channel requirements for PCI Express® Gen 4.0 align with the electrical budget and constraints as detailed in the PCI Express® CEM 4.0 Rev 1.0 and PCI Express Base Specification Rev 4.0. Exceptions or clarifications to the referenced specifications are noted in the sections below. The OCP NIC 3.0 PCIe channel requirements for PCI Express® Gen 5.0 differ from the PCI Express® CEM 5.0 Rev 0.7 for Insertion Loss Values as the loss was reduced on the OCP NIC 3.0 to allow the baseboard additional margin for SFF/TSFF implementations. The OCP NIC 3.0 LFF aligns with the specification. Refer to Section 5.3.1.2 for details.
 
4706 -7.0 dB at 16 GHz for SFF1 <> 4807 -7.0 dB at 16 GHz for SFF/TSFF1
 
4731 Note 1: OCP NIC 3.0 SFF deviates from the PCIe CEM specification on Insertion Loss Values at PCIe Gen5 speeds (32GT/s only). <> 4832 Note 1: OCP NIC 3.0 SFF/TSFF deviates from the PCIe CEM specification on Insertion Loss Values at PCIe Gen5 speeds (32GT/s only).
 
4740 Test Fixtures are designed using the PCIe CEM CLB and CBB. The fixtures host interface has been modified to the OCP connector standard and there are three versions of the fixtures for both the SFF and LFF OCP NIC 3.0 cards for Gen 3, Gen 4 and Gen 5 PCIe rates. Careful attention has been placed on these fixtures to help ensure that standard test equipment automation should work without significant modification. PCIe Gen 5 automation scripts may need to be modified as the OCP NIC 3.0 insertion loss budget differs from the PCIe CEM 5.0 32GT/s values. <> 4841 Test Fixtures are designed using the PCIe CEM CLB and CBB. The fixtures host interface has been modified to the OCP connector standard and there are three versions of the fixtures for both the SFF/TSFF and LFF OCP NIC 3.0 cards for Gen 3, Gen 4 and Gen 5 PCIe rates. Careful attention has been placed on these fixtures to help ensure that standard test equipment automation should work without significant modification. PCIe Gen 5 automation scripts may need to be modified as the OCP NIC 3.0 insertion loss budget differs from the PCIe CEM 5.0 32GT/s values.
 
4760 Figure 116: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF <> 4861 Figure 125: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF/TSFF
 
4762 Figure 117: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF <> 4863 Figure 126: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF/TSFF
 
4765 For PCIe Gen 5.0, OCP NIC 3.0 modifies the insertion loss budget on the SFF as shown in Table 59 and the test methodology may need to be adjusted to compensate for this difference. The electrical interface may be tested against the PCI Express® Architecture PHY Test Specification Revision 5.0, providing that the appropriate test fixtures from Section 5.3.2 are used and the insertion loss difference is compensated. <> 4866 For PCIe Gen 5.0, OCP NIC 3.0 modifies the insertion loss budget on the SFF/TSFF as shown in Table 59 and the test methodology may need to be adjusted to compensate for this difference. The electrical interface may be tested against the PCI Express® Architecture PHY Test Specification Revision 5.0, providing that the appropriate test fixtures from Section 5.3.2 are used and the insertion loss difference is compensated.
 
4776 The airflow in typical server systems will approach from the card edge or heatsink side of the card. This airflow direction is referred to as Hot Aisle cooling and is illustrated below in Figure 118. The term Hot Aisle refers to the card being located at the rear of the system where the local inlet airflow is preheated by the upstream system components (e.g., HDD, CPU, DIMM, etc.). <> 4877 The airflow in typical server systems will approach from the card edge or heatsink side of the card. This airflow direction is referred to as Hot Aisle cooling and is illustrated below in Figure 127. The term Hot Aisle refers to the card being located at the rear of the system where the local inlet airflow is preheated by the upstream system components (e.g., HDD, CPU, DIMM, etc.).
4777 Figure 118: Airflow Direction for Hot Aisle Cooling (SFF and LFF)   4878 Figure 127: Airflow Direction for Hot Aisle Cooling (SFF/TSFF and LFF)
 
4803 When installed in the front of a server the airflow will approach from the I/O connector (e.g., SFP, QSFP or RJ45) side of the card. This airflow direction is referred to as Cold Aisle cooling and is illustrated below in Figure 119. The term Cold Aisle refers to the card being located at the front of the system where the local inlet airflow is assumed to be the same temperature as the system inlet airflow. <> 4904 When installed in the front of a server the airflow will approach from the I/O connector (e.g., SFP, QSFP or RJ45) side of the card. This airflow direction is referred to as Cold Aisle cooling and is illustrated below in Figure 128. The term Cold Aisle refers to the card being located at the front of the system where the local inlet airflow is assumed to be the same temperature as the system inlet airflow.
4804 Figure 119: Airflow Direction for Cold Aisle Cooling (SFF and LFF)   4905 Figure 128: Airflow Direction for Cold Aisle Cooling (SFF/TSFF and LFF)
 
4832 The ASIC or controller chip is typically the highest power component on the card. Thus, as OCP NIC 3.0 cards are developed it is important to understand the ASIC cooling capability. Figure 120 below provides an estimate of the maximum ASIC power that can be supported as a function of the local inlet velocity for the SFF card in a hot aisle cooling configuration. Each curve in Figure 120 represents a different local inlet air temperature from 45 °C to 65 °C. <> 4933 The ASIC or controller chip is typically the highest power component on the card. Thus, as OCP NIC 3.0 cards are developed it is important to understand the ASIC cooling capability. Figure 129 below provides an estimate of the maximum ASIC power that can be supported as a function of the local inlet velocity for the SFF card in a hot aisle cooling configuration. Each curve in Figure 129 represents a different local inlet air temperature from 45 °C to 65 °C.
4833 Figure 120: ASIC Supportable Power for Hot Aisle Cooling – SFF   4934 Figure 129: ASIC Supportable Power for Hot Aisle Cooling – SFF
4834 The curves shown in Figure 120 were obtained using CFD analysis of a reference OCP NIC 3.0 SFF card. The reference card has a 20 mm x 20 mm ASIC with two QSFP connectors. Figure 121 shows a comparison of the 3D CAD and CFD model geometry for the reference OCP NIC 3.0 card. Additional card geometry parameters and boundary conditions used in the reference CFD analysis are summarized in Table 65. The OCP NIC 3.0 simulation was conducted within a virtual version of the test fixture defined in Section 6.4.   4935 The curves shown in Figure 129 were obtained using CFD analysis of a reference OCP NIC 3.0 SFF card. The reference card has a 20 mm x 20 mm ASIC with two QSFP connectors. Figure 130 shows a comparison of the 3D CAD and CFD model geometry for the reference OCP NIC 3.0 card. Additional card geometry parameters and boundary conditions used in the reference CFD analysis are summarized in Table 65. The OCP NIC 3.0 simulation was conducted within a virtual version of the test fixture defined in Section 6.4.
4835 Figure 121: OCP NIC 3.0 SFF Reference Design and CFD Geometry   4936 Figure 130: OCP NIC 3.0 SFF Reference Design and CFD Geometry
 
4869 An increase in the supported ASIC power or a decrease in the required airflow velocity may be achieved through heatsink size and material changes. For example, a larger heatsink or a heatsink made out of copper could improve ASIC cooling and effectively shift up the supportable power curves shown in Figure 120. <> 4970 An increase in the supported ASIC power or a decrease in the required airflow velocity may be achieved through heatsink size and material changes. For example, a larger heatsink or a heatsink made out of copper could improve ASIC cooling and effectively shift up the supportable power curves shown in Figure 129.
4870 It is important to point out that the curves shown in Figure 120 represent only the maximum ASIC power that can be supported vs. the supplied inlet velocity. Other heat loads on the card may require airflow velocities above and beyond that required to cool the ASIC. SFP or QSFP optical transceivers located downstream of the AISC will in many cases pose a greater cooling challenge than the ASIC cooling. Cooling the optical transceivers becomes even more difficult as the ASIC power is increased due to additional preheating of the air as it moves through the ASIC heatsink. OCP NIC 3.0 designers must consider all heat sources early in the design process to ensure the card thermal solution is sufficient for the feature set. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3.   4971 It is important to point out that the curves shown in Figure 129 represent only the maximum ASIC power that can be supported vs. the supplied inlet velocity. Other heat loads on the card may require airflow velocities above and beyond that required to cool the ASIC. SFP or QSFP optical transceivers located downstream of the AISC will in many cases pose a greater cooling challenge than the ASIC cooling. Cooling the optical transceivers becomes even more difficult as the ASIC power is increased due to additional preheating of the air as it moves through the ASIC heatsink. OCP NIC 3.0 designers must consider all heat sources early in the design process to ensure the card thermal solution is sufficient for the feature set. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3.
4871 Card designers must also consider the airflow capability of the server systems that the cards are targeted for use within. Figure 122 below shows the SFF ASIC supportable power curves with an overlay of three server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions.   4972 Card designers must also consider the airflow capability of the server systems that the cards are targeted for use within. Figure 131 below shows the SFF ASIC supportable power curves with an overlay of three server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions.
4872 Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling   4973 Figure 131: Server System Airflow Capability – SFF Card Hot Aisle Cooling
 
4875 Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in Aux Power Mode <> 4976 Figure 132: Server System Airflow Capability – SFF Card Hot Aisle Cooling in Aux Power Mode
      4977 TSFF Card ASIC Cooling – Hot Aisle (TBD)
      4978 This section is a work in progress.
 
4877 Figure 124 below provides an estimate of the maximum ASIC power that can be supported as a function of the local inlet velocity for the LFF card in a hot aisle cooling configuration. Each curve in Figure 124 represents a different local inlet air temperature from 45 °C to 65 °C. <> 4980 Figure 133 below provides an estimate of the maximum ASIC power that can be supported as a function of the local inlet velocity for the LFF card in a hot aisle cooling configuration. Each curve in Figure 133 represents a different local inlet air temperature from 45 °C to 65 °C.
4878 Figure 124: ASIC Supportable Power for Hot Aisle Cooling – LFF Card   4981 Figure 133: ASIC Supportable Power for Hot Aisle Cooling – LFF Card
4879 The curves shown in Figure 124 were obtained using CFD analysis of the reference OCP NIC 3.0 LFF card. The reference card has a 45 mm x 45 mm ASIC with two QSFP connectors. Additional card geometry parameters and boundary conditions used in the reference CFD analysis are summarized in Table 66. Figure 125 shows a comparison of the 3D CAD and CFD model geometry for the reference OCP NIC 3.0 card.   4982 The curves shown in Figure 133 were obtained using CFD analysis of the reference OCP NIC 3.0 LFF card. The reference card has a 45 mm x 45 mm ASIC with two QSFP connectors. Additional card geometry parameters and boundary conditions used in the reference CFD analysis are summarized in Table 66. Figure 134 shows a comparison of the 3D CAD and CFD model geometry for the reference OCP NIC 3.0 card.
4880 Figure 125: OCP NIC 3.0 LFF Reference Design and CFD Geometry   4983 Figure 134: OCP NIC 3.0 LFF Reference Design and CFD Geometry
 
4915 Figure 126 below shows the LFF ASIC supportable power curves with an overlay of three server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions. <> 5018 Figure 135 below shows the LFF ASIC supportable power curves with an overlay of three server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions.
4916 Figure 126: Server System Airflow Capability – LFF Card Hot Aisle Cooling   5019 Figure 135: Server System Airflow Capability – LFF Card Hot Aisle Cooling
 
4919 The ASIC cooling analysis for the SFF Card in the Cold Aisle configuration was conducted utilizing the same geometry and boundary conditions described in Figure 121 and Table 65 with airflow moving from I/O connector to ASIC (opposite to the Hot Aisle analysis). Figure 127 below shows the results of this analysis for the Cold Aisle cooling configuration. Each curve in Figure 127 represents a different system inlet air temperature from 25 °C to 45 °C. <> 5022 The ASIC cooling analysis for the SFF Card in the Cold Aisle configuration was conducted utilizing the same geometry and boundary conditions described in Figure 130 and Table 65 with airflow moving from I/O connector to ASIC (opposite to the Hot Aisle analysis). Figure 136 below shows the results of this analysis for the Cold Aisle cooling configuration. Each curve in Figure 136 represents a different system inlet air temperature from 25 °C to 45 °C.
 
4921 Figure 127: ASIC Supportable Power for Cold Aisle Cooling – SFF Card <> 5024 Figure 136: ASIC Supportable Power for Cold Aisle Cooling – SFF Card
4922 Similar to Figure 122 for Hot Aisle cooling, Figure 128 below shows the ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling.   5025 Similar to Figure 131 for Hot Aisle cooling, Figure 137 below shows the ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling.
4923 Figure 128: Server System Airflow Capability – SFF Cold Aisle Cooling   5026 Figure 137: Server System Airflow Capability – SFF Cold Aisle Cooling
4924 A comparison of Hot Aisle (55 °C) and Cold Aisle (35 °C) SFF ASIC cooling capability curves is shown below in Figure 129. The comparison shows the Hot Aisle ASIC cooling capability at 12 W at 150 LFM while the cold Aisle cooling capability shows support for 19 W at 150 LFM. In general, based on the reference geometry, the Cold Aisle cooling configuration allows for higher supported ASIC power at lower velocities due primarily to the lower inlet temperatures local to the OCP NIC 3.0 card when in the Cold Aisle cooling configuration.   5027 A comparison of Hot Aisle (55 °C) and Cold Aisle (35 °C) SFF ASIC cooling capability curves is shown below in Figure 138. The comparison shows the Hot Aisle ASIC cooling capability at 12 W at 150 LFM while the cold Aisle cooling capability shows support for 19 W at 150 LFM. In general, based on the reference geometry, the Cold Aisle cooling configuration allows for higher supported ASIC power at lower velocities due primarily to the lower inlet temperatures local to the OCP NIC 3.0 card when in the Cold Aisle cooling configuration.
4925 Figure 129: ASIC Supportable Power Comparison – SFF Card   5028 Figure 138: ASIC Supportable Power Comparison – SFF Card
      5029 TSFF Card ASIC Cooling – Cold Aisle (TBD)
      5030 This section is a work in progress.
 
4927 The ASIC cooling analysis for the LFF card in Cold Aisle configuration was conducted utilizing the same geometry and boundary conditions described in Figure 125 and Table 66 with airflow moving from I/O connector to ASIC (opposite to the Hot Aisle analysis). Figure 130 below shows the results of this analysis for the Cold Aisle cooling configuration. Each curve in Figure 130 represents a different system inlet air temperature from 25 °C to 45 °C. <> 5032 The ASIC cooling analysis for the LFF card in Cold Aisle configuration was conducted utilizing the same geometry and boundary conditions described in Figure 134 and Table 66 with airflow moving from I/O connector to ASIC (opposite to the Hot Aisle analysis). Figure 139 below shows the results of this analysis for the Cold Aisle cooling configuration. Each curve in Figure 139 represents a different system inlet air temperature from 25 °C to 45 °C.
4928 Figure 130: ASIC Supportable Power for Cold Aisle Cooling – LFF Card   5033 Figure 139: ASIC Supportable Power for Cold Aisle Cooling – LFF Card
4929 Similar to Figure 128 for LFF Hot Aisle cooling, Figure 131 below shows the LFF ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling.   5034 Similar to Figure 137 for LFF Hot Aisle cooling, Figure 140 below shows the LFF ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling.
4930 Figure 131: Server System Airflow Capability – LFF Cold Aisle Cooling   5035 Figure 140: Server System Airflow Capability – LFF Cold Aisle Cooling
4931 A comparison of Hot Aisle (55 °C) and Cold Aisle (35 °C) LFF ASIC cooling capability curves is shown below in Figure 132. The comparison shows the Hot Aisle ASIC cooling capability at 19 W at 150 LFM while the cold Aisle cooling capability shows support for 42 W at 150 LFM. In general, based on the reference geometry, the Cold Aisle cooling configuration allows for higher supported ASIC power at lower velocities due primarily to the lower inlet temperatures local to the OCP NIC 3.0 card when in the Cold Aisle cooling configuration.   5036 A comparison of Hot Aisle (55 °C) and Cold Aisle (35 °C) LFF ASIC cooling capability curves is shown below in Figure 141. The comparison shows the Hot Aisle ASIC cooling capability at 19 W at 150 LFM while the cold Aisle cooling capability shows support for 42 W at 150 LFM. In general, based on the reference geometry, the Cold Aisle cooling configuration allows for higher supported ASIC power at lower velocities due primarily to the lower inlet temperatures local to the OCP NIC 3.0 card when in the Cold Aisle cooling configuration.
4932 Figure 132: ASIC Supportable Power Comparison – LFF Card   5037 Figure 141: ASIC Supportable Power Comparison – LFF Card
 
4934 CFD models of the SFF and LFF cards developed for the analysis detailed in Section 6.2 are available for download on the OCP NIC 3.0 Wiki: http://www.opencompute.org/wiki/Server/Mezz <> 5039 CFD models of the SFF, TSFF and LFF cards developed for the analysis detailed in Section 6.2 are available for download on the OCP NIC 3.0 Wiki: http://www.opencompute.org/wiki/Server/Mezz
 
4938 Thermal test fixtures have been developed for SFF and LFF OCP NIC 3.0 cards. The test fixtures are intended to provide a common thermal test platform for card vendors, server vendors, and other industry groups planning to develop or utilize the OCP NIC 3.0 card form factors. Details of the thermal test fixtures are as follows: <> 5043 Thermal test fixtures have been developed for SFF, TSFF and LFF OCP NIC 3.0 cards. The test fixtures are intended to provide a common thermal test platform for card vendors, server vendors, and other industry groups planning to develop or utilize the OCP NIC 3.0 card form factors. Details of the thermal test fixtures are as follows:
 
4945 SFF fixture power connections for 3.3 V, GND, GND, 12 V <> 5050 SFF, TSFF fixture power connections for 3.3 V, GND, GND, 12 V
 
4950 Single x16 connection to server host on bottom side of the fixture PCB (SFF) <> 5055 Single x16 connection to server host on bottom side of the fixture PCB (SFF, TSFF)
 
4952 Predefined locations for fixture airflow/temperature sensors on fixture PCB silkscreen. Quantity 3x per SFF board and quantity 4x for LFF – see Figure 138 <> 5057 Predefined locations for fixture airflow/temperature sensors on fixture PCB silkscreen. Quantity 3x per SFF/TSFF board and quantity 4x for LFF – see Figure 147
 
4959 Images of the SFF thermal test fixture are shown in Figure 133 and Figure 134. The SFF fixture PCB is shown in Figure 135. Note the three candlestick sensor locations directly next to the OCP NIC 3.0 connectors. <> 5064 Images of the SFF thermal test fixture are shown in Figure 142 and Figure 143. The SFF fixture PCB is shown in Figure 144. Note the three candlestick sensor locations directly next to the OCP NIC 3.0 connectors.
4960 Figure 133: SFF Thermal Test Fixture Preliminary Design   5065 Figure 142: SFF Thermal Test Fixture Preliminary Design
4961 Figure 134: SFF Thermal Test Fixture Preliminary Design – Cover Removed   5066 Figure 143: SFF Thermal Test Fixture Preliminary Design – Cover Removed
4962 Figure 135: SFF Card Thermal Test Fixture PCB   5067 Figure 144: SFF Card Thermal Test Fixture PCB
      5068 Test Fixture for TSFF Card (TBD)
      5069 This section is a work in progress.
 
4964 Images of the LFF thermal test fixture are shown in Figure 136 and Figure 137. The LFF fixture PCB is shown in Figure 138. Note the three candlestick sensor locations directly next to the OCP NIC 3.0 connectors. <> 5071 Images of the LFF thermal test fixture are shown in Figure 145 and Figure 146. The LFF fixture PCB is shown in Figure 147. Note the three candlestick sensor locations directly next to the OCP NIC 3.0 connectors.
4965 Figure 136: LFF Card Thermal Test Fixture Design   5072 Figure 145: LFF Card Thermal Test Fixture Design
 
4967 Figure 137: LFF Card Thermal Test Fixture Design – Cover Removed <> 5074 Figure 146: LFF Card Thermal Test Fixture Design – Cover Removed
4968 Figure 138: LFF Card Thermal Test Fixture PCB   5075 Figure 147: LFF Card Thermal Test Fixture PCB
 
4970 When utilizing the OCP NIC 3.0 thermal test fixture, the wind tunnel or flow bench must be configured to push airflow for Hot Aisle cooling or to pull airflow for Cold Aisle cooling as shown in Figure 139. <> 5077 When utilizing the OCP NIC 3.0 thermal test fixture, the wind tunnel or flow bench must be configured to push airflow for Hot Aisle cooling or to pull airflow for Cold Aisle cooling as shown in Figure 148.
4971 Figure 139: Thermal Test Fixture Airflow Direction   5078 Figure 148: Thermal Test Fixture Airflow Direction
 
4975 Figure 140: External Thermocouple Placement for Cold Aisle Inlet Temperature Measurement <> 5082 Figure 149: External Thermocouple Placement for Cold Aisle Inlet Temperature Measurement
      5083 Figure 150 and Figure 151: TSFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow (TBD)
      5084 This section is a work in progress
4976 Figure 141 and Figure 142 below show the air velocity at each sensor location vs. the total fixture flow rate in CFM. The curves shown in these figures are based on the data collected from the CFD models discussed in Section 6.3. Note the error between the velocities obtained from the sensor locations vs. the velocity based on the duct cross-sectional area.   5085 Figure 152 below show the air velocity at each sensor location vs. the total fixture flow rate in CFM. The curves shown in these figures are based on the data collected from the CFD models discussed in Section 6.3. Note the error between the velocities obtained from the sensor locations vs. the velocity based on the duct cross-sectional area.
4977 Figure 141: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow   5086 Figure 150: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow
      5087 Figure 151: TSFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow (TBD)
      5088 This section is a work in progress
4978 Figure 142: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow   5089 Figure 152: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow
 
4982 Section 4.10.3 defines a number of FRU fields that may be read by the baseboard management controller (BMC). Two of these fields provide the Hot Aisle and Cold Aisle Card Cooling Tiers that may be used for open loop fan speed control. The Card Cooling Tiers relate the card local inlet temperature to the required local inlet velocity in linear feet per minute (LFM) which allows the system to set fan speeds according to the cooling requirements of the card. <> 5093 Section 4.10.3 defines several FRU fields that may be read by the baseboard management controller (BMC). Two of these fields provide the Hot Aisle and Cold Aisle Card Cooling Tiers that may be used for open loop fan speed control. The Card Cooling Tiers relate the card local inlet temperature to the required local inlet velocity in linear feet per minute (LFM) which allows the system to set fan speeds according to the cooling requirements of the card.
 
4986 A graphical view of the Card Cooling Tiers is shown in Figure 143. The Tiers range from 0 LFM to as high as 1000 LFM at 55 °C local inlet temperature. It is important to understand that the cooling tiers extend well beyond the airflow range of most server systems. As noted in Section 6.2, card designers must consider the airflow capability of the systems that the cards are to be used in when designing the card thermal solution and component placement. Figure 144 and Figure 145 below show the range of typical system capability for Hot Aisle and Cold Aisle configurations. Cards designed to these typical ranges (Tiers 1-6) will be low risk to support in most if not all server systems. Alternatively, cards that require Tier 7 or greater may still work in many server systems but may require extra validation testing, specific system slot location requirements, and potentially ambient temperature and hardware restrictions. <> 5097 A graphical view of the Card Cooling Tiers is shown in Figure 153. The Tiers range from 0 LFM to as high as 1000 LFM at 55 °C local inlet temperature. It is important to understand that the cooling tiers extend well beyond the airflow range of most server systems. As noted in Section 6.2, card designers must consider the airflow capability of the systems that the cards are to be used in when designing the card thermal solution and component placement. Figure 154 and Figure 155 below show the range of typical system capability for Hot Aisle and Cold Aisle configurations. Cards designed to these typical ranges (Tiers 1-6) will be low risk to support in most if not all server systems. Alternatively, cards that require Tier 7 or greater may still work in many server systems but may require extra validation testing, specific system slot location requirements, and potentially ambient temperature and hardware restrictions.
4987 Figure 143: Graphical View of Card Cooling Tiers   5098 Figure 153: Graphical View of Card Cooling Tiers
4988 Figure 144: Typical Operating Range for Hot Aisle Configurations   5099 Figure 154: Typical Operating Range for Hot Aisle Configurations
4989 Figure 145: Typical Operating Range for Cold Aisle Configurations   5100 Figure 155: Typical Operating Range for Cold Aisle Configurations
 
4994 The OCP NIC 3.0 shock and vibe fixture supports simultaneous testing of up to four SFF, or four LFF cards. The SFF fixture accepts card configurations that utilize the pull tab, ejector lever and internal lock mechanisms. The LFF fixture only accepts the single latch faceplate. <> 5105 The OCP NIC 3.0 shock and vibe fixture supports simultaneous testing of up to four SFF/TSFF, or four LFF cards. The SFF/TSFF fixture accepts card configurations that utilize the pull tab, ejector lever and internal lock mechanisms. The LFF fixture only accepts the single latch faceplate.
4995 The fixture is comprised of a universal baseplate that allows for attaching SFF or LFF rail guides and simulated chassis faceplates. The baseplate includes an industry standard vibration table hole pattern for securing the UUT for test. Figure 146 and Figure 147 show the SFF and LFF fixtures, respectively.   5106 The fixture is comprised of a universal baseplate that allows for attaching SFF/TSFF or LFF rail guides and simulated chassis faceplates. The baseplate includes an industry standard vibration table hole pattern for securing the UUT for test. Figure 156 and Figure 157 show the SFF/TSFF and LFF fixtures, respectively.
 
4997 Figure 146: SFF Shock and Vibe Fixture <> 5108 Figure 156: SFF/TSFF Shock and Vibe Fixture
4998 Figure 147: LFF Shock and Vibe Fixture   5109 Figure 157: LFF Shock and Vibe Fixture
 
5035 Figure 148: Dye and Pull Type Locations <> 5146 Figure 158: Dye and Pull Type Locations
 
5037 Dye coverage of >50% (“D” and “E” in Figure 149) of any Type 2 or Type 3 BGA cracks are present in the test sample. <> 5148 Dye coverage of >50% (“D” and “E” in Figure 159) of any Type 2 or Type 3 BGA cracks are present in the test sample.
 
5039 Figure 149: Dye Coverage Percentage <> 5150 Figure 159: Dye Coverage Percentage
 
5097 UL 60950-1/CSA C22.2 No. 60950-1-07, 2nd Edition + Amendment 1 + Amendment 2, dated 2011/12/19. <> 5208 UL 62368-1 and CAN/CSA C22.2 No. 62368-1-14, 3rd Edition. Audio/video, information and communication technology equipment Part 1: Safety requirements, dated 2019/12/13.
5098 The Bi-National Standard for Safety of Information Technology Equipment, EN60950-1: 2006+A11:2009+A1:2010+A12:2010+A2:2013      
5099 IEC 60950-1 (Ed 2) + A1 + A2.      
5100 IEC 62368-1 may also be co-reported depending on region      
 
5278 Offset 19/20 – Add Hot/Cold Aisle tier for use with active cables.Offset 21/22 – Add Reference module power and temperature level.Offset 23 – Add reference active cooling fan fail tier requirement.Offset 31 – Defined "controller" as a SMBus connected device in the context of the FRU UDID. <> 5386 Offset 19/20 – Add Hot/Cold Aisle tier for use with active cables.Offset 21/22 – Add Reference module power and temperature level.Offset 23 – Add reference active cooling fan fail tier requirement.Offset 31 – Defined “controller” as a SMBus connected device in the context of the FRU UDID.
 
5296 - Section 4.3 - Clarified MC MAC address provisioning requirements for multi-host capable cards as the maximum number of supported hosts. <> 5404 - Section 4.3 – Clarified MC MAC address provisioning requirements for multi-host capable cards as the maximum number of supported hosts.
 
5304 - Section 3.11 - Change the max TAPL / TMPL (AUX_PWR_EN to NIC_PWR_GOOD and MAIN_PWR_EN to NIC_PWR_GOOD) parameters from 25ms to 50ms. <> 5412 - Section 3.11 – Change the max TAPL / TMPL (AUX_PWR_EN to NIC_PWR_GOOD and MAIN_PWR_EN to NIC_PWR_GOOD) parameters from 25ms to 50ms.
 
5336 Document release - version R1v00 <> 5444 Document release – version R1v00
 
5345 - Section 2.5.1, 2.5.2 – Figure 24 & 29 - Update PCB break off note #3 to include feature max tolerances.- Section 2.8.2 – Figure 40 – Updated dimension notation with parenthesis and add center line labeled as CL DATUM H for consistency across form-factor figures. <> 5453 - Section 2.5.1, 2.5.2 – Figure 24 & 29 – Update PCB break off note #3 to include feature max tolerances.- Section 2.8.2 – Figure 40 – Updated dimension notation with parenthesis and add center line labeled as CL DATUM H for consistency across form-factor figures.
 
5360 Offset 3 - Add new FRU record version for spec version 1.1. <> 5468 Offset 3 – Add new FRU record version for spec version 1.1.
5361 Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19.   5469 Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables – similar to offset 19.
5362 Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19.   5470 Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables – similar to offset 19.
 
5372 Document release - version R1.1.0 <> 5480 Document release – version R1.1.0
 
    -+ 5483 OCP NIC 3.0 Subgroup
      5484 - General – Changed “SFF” references to “SFF/TSFF” where applicable.
      5485 - General – Format all tables with repeated headers when they span multiple pages
      5486 - Section 1.2 – Added Molex to the acknowledgements section. Changed NVIDIA to NVIDIA Corporation.
      5487 - Section 1.4 – Added TSFF, OSFP-RHS and QSFP-DD to the acronyms section.
      5488 - Section 1.6, 2.1.1 – Added text for TSFF and clarify TSFF shares the same mechanical outline as SFF. Add representative TSFF diagram.
      5489 - Section 1.7.1 – Added TSFF to the OCP NIC 3.0 Form Factor Dimensions table; add Max Z-height information. Added note that SFF may fit in TSFF slot and in LFF slot, but the combination (and support mechanisms) are outside of the scope of the current specification.
      5490 - Section 1.7.2.x – Updated text "Up to PCIe Gen 5 (32 GT/s) support"- Section 2.1 - Add TSFF. Add notes that actual cooling capacity for a SFF/TSFF/LFF card is dependent on the ambient conditions over the NIC.- Section 2.1.x – Clarified that faceplates are attached to the PCBA at the time of manufacture.- Section 2.1.1 – Add TSFF faceplate views to Figure 7.
      5491 - Section 2.2 – Add QSFP-DD, OSFP-RHS in Line side implementation table. Add QSFP-DD, OSFP to standards cross reference table.- Section 2.3 – Add TSFF PBA exploded views to Figure 13.
      5492 - Section 2.4.1, 2.4.2 – Updated faceplate subassembly drawing and BOM callouts for SFF/TSFF.
      5493 - Section 2.4.4 – Added TSFF generic faceplate drawings. Drawings only contain dimensional deltas from SFF.
      5494 - Section 2.5.2 – Added TSFF keep out zones. Drawings only contain dimensional deltas from SFF.- Section 2.8.5 - Replaced Figure 56 - SFF Baseboard Chassis CTF dimensions (Rear Rail Guide View) as it was clipped in the previous release.
      5495 - Section 2.8.6, 2.8.7, 2.8.8, 2.8.9 – Added TSFF CTF dimensions for pull tab, ejector and internal lock board dimensions. Add TSFF baseboard CTF dimensions. Drawings only contain dimensional deltas from SFF.- Section 2.10 – Added TSFF Generic faceplate assembly CAD.- Section 3.4.1 – Clarified that hosts with unused PERST[1:5]# signals shall implement at 10kOhm pull down on the baseboard to prevent floating nets.
      5496 - Section 3.4.2, 3.5.4 – Clarified that the BIF[2:0]# pins shall not change states after AUX_PWR_EN is asserted.
      5497 - Section 3.4.4 – Clarified that the RBT_ISOLATE# signal shall not change state even when the NIC_PWR_GOOD signal is in the don't care state.
      5498 - Section 3.7.3 – Added note regarding the use of light pipes above I/O cage assemblies for TSFF and cage implementations.
      5499 - Section 3.11 – Clarified power down sequencing diagram - +12V_EDGE may optionally be disabled in ID Mode. This mirrors the same behavior for the power up sequencing diagram.- Section 4.4 – Clarified self-shutdown threshold. Recommended value should be set to above the Upper Fatal threshold.
      5500 - Section 4.10.3 – FRU Updates:Offset 3 – Add definition for version 1.2.0 compatible FRU.Offset 29 – Add definition for Self-shutdown Temperature threshold.
      5501 - Section 5.1 – Added note stating the SFF and TSFF timing parameters are the same since the cards may share the same PBA.
      5502 - Section 6.2.2, 6.2.5 – Added placeholder headings for the hot and cold aisle cooling graphs for TSFF.
      5503 - Section 6.4.2 – Added placeholder heading for the TSFF thermal test fixture.
      5504 - Section 6.4.5 – Added placeholder figure headings for the TSFF candlestick air velocity vs volume flow graphs.
      5505 - Section 7.1.3 – Updated Safety requirements. 60950-1 was withdrawn as of 12/20/2020. 62368-1 replaced 60950-1.
      5506 1.2.0
      5507 08/20/2021
 
    -+ 5568 8/20/2021
      5569 Offset 3 – Add definition for version 1.2.0 compatible FRU.Offset 29 – Add definition for Self-shutdown Temperature threshold.
      5570 1.2.0