| 2 | Version 1.0.9 | <> | 2 | Version 1.1.0 |
| 102 | 3.8.3 Aux Power Mode (S5) 146 | <> | 102 | 3.8.3 Aux Power Mode 147 |
| 103 | 3.8.4 Main Power Mode (S0) 147 | 103 | 3.8.4 Main Power Mode 147 | |
| 105 | 3.9 Power Supply Rail Requirements and Slot Power Envelopes 148 | <> | 105 | 3.9 Power Supply Rail Requirements and Slot Power Envelopes 149 |
| 106 | 3.10 Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails 149 | 106 | 3.10 Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails 150 | |
| 107 | 3.11 Power Sequence Timing Requirements 150 | 107 | 3.11 Power Sequence Timing Requirements 151 | |
| 108 | 3.12 Digital I/O Specifications 154 | 108 | 3.12 Digital I/O Specifications 155 | |
| 109 | 4 Management and Pre-OS Requirements 155 | 109 | 4 Management and Pre-OS Requirements 156 | |
| 110 | 4.1 Sideband Management Interface and Transport 155 | 110 | 4.1 Sideband Management Interface and Transport 156 | |
| 111 | 4.2 NC-SI Traffic 156 | 111 | 4.2 NC-SI Traffic 157 | |
| 112 | 4.3 Management Controller (MC) MAC Address Provisioning 156 | 112 | 4.3 Management Controller (MC) MAC Address Provisioning 157 | |
| 113 | 4.4 ASIC Die Temperature Reporting 158 | 113 | 4.4 ASIC Die Temperature Reporting 159 | |
| 114 | 4.5 Power Consumption Reporting 161 | 114 | 4.5 Power Consumption Reporting 162 | |
| 115 | 4.6 Pluggable Transceiver Module Status and Temperature Reporting 162 | 115 | 4.6 Pluggable Transceiver Module Status and Temperature Reporting 163 | |
| 116 | 4.7 Management and Pre-OS Firmware Inventory and Update 162 | 116 | 4.7 Management and Pre-OS Firmware Inventory and Update 163 | |
| 117 | 4.7.1 Secure Firmware 162 | 117 | 4.7.1 Secure Firmware 163 | |
| 118 | 4.7.2 Firmware Inventory 163 | 118 | 4.7.2 Firmware Inventory 164 | |
| 119 | 4.7.3 Firmware Inventory and Update in Multi-Host Environments 163 | 119 | 4.7.3 Firmware Inventory and Update in Multi-Host Environments 164 | |
| 120 | 4.8 NC-SI Package Addressing and Hardware Arbitration Requirements 164 | 120 | 4.8 NC-SI Package Addressing and Hardware Arbitration Requirements 165 | |
| 121 | 4.8.1 NC-SI over RBT Package Addressing 164 | 121 | 4.8.1 NC-SI over RBT Package Addressing 165 | |
| 122 | 4.8.2 Arbitration Ring Connections 164 | 122 | 4.8.2 Arbitration Ring Connections 165 | |
| 123 | 4.9 SMBus 2.0 Addressing Requirements 164 | 123 | 4.9 SMBus 2.0 Addressing Requirements 165 | |
| 124 | 4.9.1 SMBus Address Map 165 | 124 | 4.9.1 SMBus Address Map 166 | |
| 125 | 4.10 FRU EEPROM 165 | 125 | 4.10 FRU EEPROM 166 | |
| 126 | 4.10.1 FRU EEPROM Addressing and Size 165 | 126 | 4.10.1 FRU EEPROM Addressing and Size 166 | |
| 127 | 4.10.2 FRU EEPROM Write Protection 167 | 127 | 4.10.2 FRU EEPROM Write Protection 168 | |
| 128 | 4.10.3 FRU EEPROM Content Requirements 167 | 128 | 4.10.3 FRU EEPROM Content Requirements 168 | |
| 129 | 4.10.4 FRU Template 174 | 129 | 4.10.4 FRU Template 175 | |
| 130 | 5 Routing Guidelines and Signal Integrity Considerations 174 | 130 | 5 Routing Guidelines and Signal Integrity Considerations 175 | |
| 131 | 5.1 NC-SI over RBT 174 | 131 | 5.1 NC-SI over RBT 175 | |
| 132 | 5.1.1 SFF Baseboard Requirements 176 | 132 | 5.1.1 SFF Baseboard Requirements 177 | |
| 133 | 5.1.2 LFF Baseboard Requirements 176 | 133 | 5.1.2 LFF Baseboard Requirements 177 | |
| 134 | 5.1.3 SFF OCP NIC 3.0 Card Requirements 177 | 134 | 5.1.3 SFF OCP NIC 3.0 Card Requirements 178 | |
| 135 | 5.1.4 LFF OCP NIC 3.0 Card Requirements 178 | 135 | 5.1.4 LFF OCP NIC 3.0 Card Requirements 179 | |
| 136 | 5.2 SMBus 2.0 178 | 136 | 5.2 SMBus 2.0 179 | |
| 137 | 5.3 PCIe 179 | 137 | 5.3 PCIe 180 | |
| 138 | 5.3.1 Channel Requirements 179 | 138 | 5.3.1 Channel Requirements 180 | |
| 139 | 5.3.1.1 REFCLK requirements 179 | 139 | 5.3.1.1 REFCLK requirements 180 | |
| 140 | 5.3.1.2 Add-in Card Electrical Budgets 179 | 140 | 5.3.1.2 Add-in Card Electrical Budgets 180 | |
| 141 | 5.3.1.3 Baseboard Channel Budget 180 | 141 | 5.3.1.3 Baseboard Channel Budget 181 | |
| 142 | 5.3.1.4 SFF-TA-1002 Connector Channel Budget 180 | 142 | 5.3.1.4 SFF-TA-1002 Connector Channel Budget 181 | |
| 143 | 5.3.1.5 Differential Impedance (Informative) 180 | 143 | 5.3.1.5 Differential Impedance (Informative) 181 | |
| 144 | 5.3.2 Test Fixtures 180 | 144 | 5.3.2 Test Fixtures 181 | |
| 145 | 5.3.2.1 Compliance Load Board (CLB) 180 | 145 | 5.3.2.1 Compliance Load Board (CLB) 181 | |
| 146 | 5.3.2.2 Compliance Baseboard (CBB) 182 | 146 | 5.3.2.2 Compliance Baseboard (CBB) 183 | |
| 147 | 5.3.3 Test Methodology 182 | 147 | 5.3.3 Test Methodology 183 | |
| 148 | 5.3.3.1 Test Setup 182 | 148 | 5.3.3.1 Test Setup 183 | |
| 149 | 6 Thermal and Environmental 184 | 149 | 6 Thermal and Environmental 185 | |
| 150 | 6.1 Airflow Direction 184 | 150 | 6.1 Airflow Direction 185 | |
| 151 | 6.1.1 Hot Aisle Cooling 184 | 151 | 6.1.1 Hot Aisle Cooling 185 | |
| 152 | 6.1.2 Cold Aisle Cooling 185 | 152 | 6.1.2 Cold Aisle Cooling 186 | |
| 153 | 6.2 Thermal Design Guidelines 186 | 153 | 6.2 Thermal Design Guidelines 187 | |
| 154 | 6.2.1 SFF Card ASIC Cooling – Hot Aisle 186 | 154 | 6.2.1 SFF Card ASIC Cooling – Hot Aisle 187 | |
| 155 | 6.2.2 LFF Card ASIC Cooling – Hot Aisle 190 | 155 | 6.2.2 LFF Card ASIC Cooling – Hot Aisle 191 | |
| 156 | 6.2.3 SFF Card ASIC Cooling – Cold Aisle 192 | 156 | 6.2.3 SFF Card ASIC Cooling – Cold Aisle 193 | |
| 157 | 6.2.4 LFF Card ASIC Cooling – Cold Aisle 195 | 157 | 6.2.4 LFF Card ASIC Cooling – Cold Aisle 196 | |
| 158 | 6.3 Thermal Simulation (CFD) Modeling 197 | 158 | 6.3 Thermal Simulation (CFD) Modeling 198 | |
| 159 | 6.4 Thermal Test Fixture 197 | 159 | 6.4 Thermal Test Fixture 198 | |
| 160 | 6.4.1 Test Fixture for SFF Card 198 | 160 | 6.4.1 Test Fixture for SFF Card 199 | |
| 161 | 6.4.2 Test Fixture for LFF Card 200 | 161 | 6.4.2 Test Fixture for LFF Card 201 | |
| 162 | 6.4.3 Test Fixture Airflow Direction 202 | 162 | 6.4.3 Test Fixture Airflow Direction 203 | |
| 163 | 6.4.4 Thermal Test Fixture Candlestick Sensors 202 | 163 | 6.4.4 Thermal Test Fixture Candlestick Sensors 203 | |
| 164 | 6.5 Card Sensor Requirements 204 | 164 | 6.5 Card Sensor Requirements 205 | |
| 165 | 6.6 Card Cooling Tiers 204 | 165 | 6.6 Card Cooling Tiers 205 | |
| 166 | 6.7 Non-Operational Shock & Vibration Testing 206 | 166 | 6.7 Non-Operational Shock & Vibration Testing 207 | |
| 167 | 6.7.1 Shock & Vibe Test Fixture 206 | 167 | 6.7.1 Shock & Vibe Test Fixture 207 | |
| 168 | 6.7.2 Test Procedure 207 | 168 | 6.7.2 Test Procedure 208 | |
| 169 | 6.8 Dye and Pull Test Method 209 | 169 | 6.8 Dye and Pull Test Method 210 | |
| 170 | 6.9 Gold Finger Plating Requirements 211 | 170 | 6.9 Gold Finger Plating Requirements 212 | |
| 171 | 6.9.1 Host Side Gold Finger Plating Requirements 211 | 171 | 6.9.1 Host Side Gold Finger Plating Requirements 212 | |
| 172 | 6.9.2 Line Side Gold Finger Durability Requirements 211 | 172 | 6.9.2 Line Side Gold Finger Durability Requirements 212 | |
| 173 | 7 Regulatory 212 | 173 | 7 Regulatory 213 | |
| 174 | 7.1 Required Compliance 212 | 174 | 7.1 Required Compliance 213 | |
| 175 | 7.1.1 Required Environmental Compliance 212 | 175 | 7.1.1 Required Environmental Compliance 213 | |
| 176 | 7.1.2 Required EMC Compliance 212 | 176 | 7.1.2 Required EMC Compliance 213 | |
| 177 | 7.1.3 Required Product Safety Compliance 213 | 177 | 7.1.3 Required Product Safety Compliance 214 | |
| 178 | 7.1.4 Required Immunity (ESD) Compliance 213 | 178 | 7.1.4 Required Immunity (ESD) Compliance 214 | |
| 179 | 7.2 Recommended Compliance 214 | 179 | 7.2 Recommended Compliance 215 | |
| 180 | 7.2.1 Recommended Environmental Compliance 214 | 180 | 7.2.1 Recommended Environmental Compliance 215 | |
| 181 | 7.2.2 Recommended EMC Compliance 214 | 181 | 7.2.2 Recommended EMC Compliance 215 | |
| 182 | 8 Revision History 215 | 182 | 8 Revision History 216 | |
| 183 | 8.1 Document Revision History 215 | 183 | 8.1 Document Revision History 216 | |
| 184 | 8.2 FRU Content Revision History 222 | 184 | 8.2 FRU Content Revision History 224 | |
| 292 | Figure 107: Power-Up Sequencing – Normal Operation 150 | <> | 292 | Figure 107: Power-Up Sequencing – Normal Operation 151 |
| 293 | Figure 108: Power-Down Sequencing – Normal Operation 151 | 293 | Figure 108: Power-Down Sequencing – Normal Operation 152 | |
| 294 | Figure 109: Programming Mode Sequencing 152 | 294 | Figure 109: Programming Mode Sequencing 153 | |
| 295 | Figure 110: FRU EEPROM Writes with Double Byte Addressing 166 | 295 | Figure 110: FRU EEPROM Writes with Double Byte Addressing 167 | |
| 296 | Figure 111: FRU EEPROM Reads with Double Byte Addressing 166 | 296 | Figure 111: FRU EEPROM Reads with Double Byte Addressing 167 | |
| 297 | Figure 112: FRU Update Flow 167 | 297 | Figure 112: FRU Update Flow 168 | |
| 298 | Figure 113: NC-SI over RBT Timing Budget Topology 175 | 298 | Figure 113: NC-SI over RBT Timing Budget Topology 177 | |
| 299 | Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer 178 | 299 | Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer 179 | |
| 300 | Figure 115: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer 178 | 300 | Figure 115: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer 179 | |
| 301 | Figure 116: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF 180 | 301 | Figure 116: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF 181 | |
| 302 | Figure 117: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF 182 | 302 | Figure 117: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF 183 | |
| 303 | Figure 118: Airflow Direction for Hot Aisle Cooling (SFF and LFF) 184 | 303 | Figure 118: Airflow Direction for Hot Aisle Cooling (SFF and LFF) 185 | |
| 304 | Figure 119: Airflow Direction for Cold Aisle Cooling (SFF and LFF) 185 | 304 | Figure 119: Airflow Direction for Cold Aisle Cooling (SFF and LFF) 186 | |
| 305 | Figure 120: ASIC Supportable Power for Hot Aisle Cooling – SFF 186 | 305 | Figure 120: ASIC Supportable Power for Hot Aisle Cooling – SFF 187 | |
| 306 | Figure 121: OCP NIC 3.0 SFF Reference Design and CFD Geometry 187 | 306 | Figure 121: OCP NIC 3.0 SFF Reference Design and CFD Geometry 188 | |
| 307 | Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling 188 | 307 | Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling 189 | |
| 308 | Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode 189 | 308 | Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in Aux Power Mode 190 | |
| 309 | Figure 124: ASIC Supportable Power for Hot Aisle Cooling – LFF Card 190 | 309 | Figure 124: ASIC Supportable Power for Hot Aisle Cooling – LFF Card 191 | |
| 310 | Figure 125: OCP NIC 3.0 LFF Reference Design and CFD Geometry 190 | 310 | Figure 125: OCP NIC 3.0 LFF Reference Design and CFD Geometry 191 | |
| 311 | Figure 126: Server System Airflow Capability – LFF Card Hot Aisle Cooling 192 | 311 | Figure 126: Server System Airflow Capability – LFF Card Hot Aisle Cooling 193 | |
| 312 | Figure 127: ASIC Supportable Power for Cold Aisle Cooling – SFF Card 193 | 312 | Figure 127: ASIC Supportable Power for Cold Aisle Cooling – SFF Card 194 | |
| 313 | Figure 128: Server System Airflow Capability – SFF Cold Aisle Cooling 194 | 313 | Figure 128: Server System Airflow Capability – SFF Cold Aisle Cooling 195 | |
| 314 | Figure 129: ASIC Supportable Power Comparison – SFF Card 194 | 314 | Figure 129: ASIC Supportable Power Comparison – SFF Card 195 | |
| 315 | Figure 130: ASIC Supportable Power for Cold Aisle Cooling – LFF Card 195 | 315 | Figure 130: ASIC Supportable Power for Cold Aisle Cooling – LFF Card 196 | |
| 316 | Figure 131: Server System Airflow Capability – LFF Cold Aisle Cooling 196 | 316 | Figure 131: Server System Airflow Capability – LFF Cold Aisle Cooling 197 | |
| 317 | Figure 132: ASIC Supportable Power Comparison – LFF Card 196 | 317 | Figure 132: ASIC Supportable Power Comparison – LFF Card 197 | |
| 318 | Figure 133: SFF Thermal Test Fixture Preliminary Design 198 | 318 | Figure 133: SFF Thermal Test Fixture Preliminary Design 199 | |
| 319 | Figure 134: SFF Thermal Test Fixture Preliminary Design – Cover Removed 199 | 319 | Figure 134: SFF Thermal Test Fixture Preliminary Design – Cover Removed 200 | |
| 320 | Figure 135: SFF Card Thermal Test Fixture PCB 199 | 320 | Figure 135: SFF Card Thermal Test Fixture PCB 200 | |
| 321 | Figure 136: LFF Card Thermal Test Fixture Design 200 | 321 | Figure 136: LFF Card Thermal Test Fixture Design 201 | |
| 322 | Figure 137: LFF Card Thermal Test Fixture Design – Cover Removed 200 | 322 | Figure 137: LFF Card Thermal Test Fixture Design – Cover Removed 201 | |
| 323 | Figure 138: LFF Card Thermal Test Fixture PCB 201 | 323 | Figure 138: LFF Card Thermal Test Fixture PCB 202 | |
| 324 | Figure 139: Thermal Test Fixture Airflow Direction 202 | 324 | Figure 139: Thermal Test Fixture Airflow Direction 203 | |
| 325 | Figure 140: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 203 | 325 | Figure 140: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 204 | |
| 326 | Figure 141: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 203 | 326 | Figure 141: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 204 | |
| 327 | Figure 142: Graphical View of Card Cooling Tiers 205 | 327 | Figure 142: Graphical View of Card Cooling Tiers 206 | |
| 328 | Figure 143: Typical Operating Range for Hot Aisle Configurations 205 | 328 | Figure 143: Typical Operating Range for Hot Aisle Configurations 206 | |
| 329 | Figure 144: Typical Operating Range for Cold Aisle Configurations 206 | 329 | Figure 144: Typical Operating Range for Cold Aisle Configurations 207 | |
| 330 | Figure 145: SFF Shock and Vibe Fixture 207 | 330 | Figure 145: SFF Shock and Vibe Fixture 208 | |
| 331 | Figure 146: LFF Shock and Vibe Fixture 207 | 331 | Figure 146: LFF Shock and Vibe Fixture 208 | |
| 332 | Figure 147: Dye and Pull Type Locations 210 | 332 | Figure 147: Dye and Pull Type Locations 211 | |
| 333 | Figure 148: Dye Coverage Percentage 210 | 333 | Figure 148: Dye Coverage Percentage 211 | |
| 357 | Table 23: Pin Descriptions – PCIe 87 | <> | 357 | Table 23: Pin Descriptions – PCIe 88 |
| 376 | Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes 148 | <> | 376 | Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes 149 |
| 377 | Table 43: Power Sequencing Parameters 152 | 377 | Table 43: Power Sequencing Parameters 153 | |
| 378 | Table 44: Digital I/O DC specifications 154 | 378 | Table 44: Digital I/O DC specifications 155 | |
| 379 | Table 45: Digital I/O AC specifications 154 | 379 | Table 45: Digital I/O AC specifications 155 | |
| 380 | Table 46: OCP NIC 3.0 Management Implementation Definitions 155 | 380 | Table 46: OCP NIC 3.0 Management Implementation Definitions 156 | |
| 381 | Table 47: Sideband Management Interface and Transport Requirements 155 | 381 | Table 47: Sideband Management Interface and Transport Requirements 156 | |
| 382 | Table 48: NC-SI Traffic Requirements 156 | 382 | Table 48: NC-SI Traffic Requirements 157 | |
| 383 | Table 49: MC MAC Address Provisioning Requirements 156 | 383 | Table 49: MC MAC Address Provisioning Requirements 157 | |
| 384 | Table 50: Threshold Severity Level vs Example Threshold Values 159 | 384 | Table 50: Threshold Severity Level vs Example Threshold Values 160 | |
| 385 | Table 51: Temperature Reporting Requirements 159 | 385 | Table 51: Temperature Reporting Requirements 160 | |
| 386 | Table 52: Power Consumption Reporting Requirements 161 | 386 | Table 52: Power Consumption Reporting Requirements 162 | |
| 387 | Table 53: Pluggable Module Status Reporting Requirements 162 | 387 | Table 53: Pluggable Module Status Reporting Requirements 163 | |
| 388 | Table 54: Management and Pre-OS Firmware Inventory and Update Requirements 162 | 388 | Table 54: Management and Pre-OS Firmware Inventory and Update Requirements 163 | |
| 389 | Table 55: Slot_ID[1:0] to Package ID[2:0] Mapping 164 | 389 | Table 55: Slot_ID[1:0] to Package ID[2:0] Mapping 165 | |
| 390 | Table 56: FRU EEPROM Address Map 165 | 390 | Table 56: FRU EEPROM Address Map 166 | |
| 391 | Table 57: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00 168 | 391 | Table 57: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00 169 | |
| 392 | Table 58: NC-SI over RBT Timing Parameters 175 | 392 | Table 58: NC-SI over RBT Timing Parameters 176 | |
| 393 | Table 59: PCIe Electrical Budgets 179 | 393 | Table 59: PCIe Electrical Budgets 180 | |
| 394 | Table 60: PCIe Test Fixtures for OCP NIC 3.0 180 | 394 | Table 60: PCIe Test Fixtures for OCP NIC 3.0 181 | |
| 395 | Table 61: Hot Aisle Air Temperature Boundary Conditions 185 | 395 | Table 61: Hot Aisle Air Temperature Boundary Conditions 186 | |
| 396 | Table 62: Hot Aisle Airflow Boundary Conditions 185 | 396 | Table 62: Hot Aisle Airflow Boundary Conditions 186 | |
| 397 | Table 63: Cold Aisle Air Temperature Boundary Conditions 185 | 397 | Table 63: Cold Aisle Air Temperature Boundary Conditions 186 | |
| 398 | Table 64: Cold Aisle Airflow Boundary Conditions 186 | 398 | Table 64: Cold Aisle Airflow Boundary Conditions 187 | |
| 399 | Table 65: Reference OCP NIC 3.0 SFF Card Geometry 187 | 399 | Table 65: Reference OCP NIC 3.0 SFF Card Geometry 188 | |
| 400 | Table 66: Reference OCP NIC 3.0 LFF Card Geometry 191 | 400 | Table 66: Reference OCP NIC 3.0 LFF Card Geometry 192 | |
| 401 | Table 67: Card Cooling Tier Definitions (LFM) 204 | 401 | Table 67: Card Cooling Tier Definitions (LFM) 205 | |
| 402 | Table 68: Random Vibration Testing 1.88 GRMS Profile 208 | 402 | Table 68: Random Vibration Testing 1.88 GRMS Profile 209 | |
| 403 | Table 69: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location 212 | 403 | Table 69: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location 213 | |
| 404 | Table 70: Safety Requirements 213 | 404 | Table 70: Safety Requirements 214 | |
| 405 | Table 71: Immunity (ESD) Requirements 213 | 405 | Table 71: Immunity (ESD) Requirements 214 | |
| 2728 | Note: The OCP NIC 3.0 card shall implement protection methods to prevent leakage or low impedance paths between the VAUX and VMAIN power domains in the event that a powered-down NIC is physically present in a powered-up baseboard. This specification provides example isolation implementations in the signal description text and appropriate figures. OCP NIC 3.0 implementers may choose to do a different implementation as long as the isolation requirements are met and the same result is achieved. | <> | 2728 | Note 1: The OCP NIC 3.0 card shall implement protection methods to prevent leakage or low impedance paths between the VAUX and VMAIN power domains if a powered-down NIC is physically present in a powered-up baseboard. This specification provides example isolation implementations in the signal description text and appropriate figures. OCP NIC 3.0 implementers may choose to do a different implementation as long as the isolation requirements are met and the same result is achieved. |
| 2729 | Note 2: The terms Aux Power Mode and Main Power Mode are used within this specification and define the corresponding ACPI power states of the system. | |||
| 2730 | Aux Power Mode corresponds to the S5 ACPI power state and may also include ACPI power states S3 or S4 depending on the implementation. In Aux Power Mode, AUX_PWR_EN==1, and MAIN_PWR_EN==0. | |||
| 2731 | Main Power Mode corresponds to the S0 ACPI power state on the system and may also correspond to ACPI power state S1 depending on the implementation. In Main Power Mode, AUX_PWR_EN==1, and MAIN_PWR_EN==1. | |||
| 2963 | For OCP NIC 3.0 cards, this signal shall be connected between the endpoint silicon WAKE# pin(s) and the card edge through an isolation buffer. The WAKE# signal shall not assert until the PCIe card is in the D3 state according to the PCIe CEM specification to prevent false WAKE# events. For OCP NIC 3.0, the WAKE# pin shall be buffered or otherwise isolated from the host until the aux voltage source is present. Examples of this are shown in Section 3.5.5 by gating via an on-board “AUX_PWR_GOOD” signal to indicate all the NIC AUX power rails are stable. The PCIe CEM specification also shows an example in the WAKE# signal section. | <> | 2966 | For OCP NIC 3.0 cards, this signal shall be connected between the endpoint silicon WAKE# pin(s) and the card edge through an isolation buffer. The WAKE# signal shall not assert until the PCIe card is in the D3 state according to the PCIe CEM specification to prevent false WAKE# events. For OCP NIC 3.0, the WAKE# pin shall be buffered or otherwise isolated from the host until the aux voltage source is present. Examples of this are shown in Section 3.5.5 by gating via an on-board “AUX_PWR_GOOD” signal to indicate all the NIC Aux power rails are stable. The PCIe CEM specification also shows an example in the WAKE# signal section. |
| 3014 | For OCP NIC 3.0 cards, these signals shall connect to the endpoint bifurcation pins if it is supported. The BIF[2:0]# signals shall be left as no connects if end point bifurcation is not supported. The value of the BIF[2:0]# pins are latched by the OCP NIC 3.0 card upon entering the AUX power mode state (when AUX_PWR_EN=1 and NIC_PWR_GOOD=1). | <> | 3017 | For OCP NIC 3.0 cards, these signals shall connect to the endpoint bifurcation pins if it is supported. The BIF[2:0]# signals shall be left as no connects if end point bifurcation is not supported. The value of the BIF[2:0]# pins are latched by the OCP NIC 3.0 card upon entering Aux Power Mode (when AUX_PWR_EN=1 and NIC_PWR_GOOD=1). |
| 3047 | Note: The RBT pins must provide the ability to be isolated on the baseboard side when AUX_PWR_EN=0 or when (AUX_PWR_EN=1 and NIC_PWR_GOOD=0). The RBT pins shall remain isolated until the power state machine has transitioned to AUX power mode or to Main Power Mode along with a valid indication of NIC_PWR_GOOD. This prevents a leakage path through unpowered silicon. The RBT REF_CLK must also be disabled until AUX_PWR_EN=1 and NIC_PWR_GOOD=1. Example buffering implementations are shown in Figure 85 and Figure 86. The isolator shall be controlled on the baseboard with a signal called RBT_ISOLATE#. | <> | 3050 | Note: The RBT pins must provide the ability to be isolated on the baseboard side when AUX_PWR_EN=0 or when (AUX_PWR_EN=1 and NIC_PWR_GOOD=0). The RBT pins shall remain isolated until the power state machine has transitioned to Aux Power Mode or to Main Power Mode along with a valid indication of NIC_PWR_GOOD. This prevents a leakage path through unpowered silicon. The RBT REF_CLK must also be disabled until AUX_PWR_EN=1 and NIC_PWR_GOOD=1. Example buffering implementations are shown in Figure 85 and Figure 86. The isolator shall be controlled on the baseboard with a signal called RBT_ISOLATE#. |
| 3059 | For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the Primary Connector OCP bay. The RBT_REF_CLK shall not be driven until the card has transitioned into AUX Power Mode. The RBT_REF_CLK shall be continuous once it has started. | <> | 3062 | For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the Primary Connector OCP bay. The RBT_REF_CLK shall not be driven until the card has transitioned into Aux Power Mode. The RBT_REF_CLK shall be continuous once it has started. |
| 3302 | When high, FAN_ON_AUX shall request the system fan to be enabled for extra cooling in the S5 state. | <> | 3305 | When high, FAN_ON_AUX shall request the system fan to be enabled for extra cooling in Aux Power Mode. |
| 3305 | 0b0 – The system fan is not requested/off in S5. | <> | 3308 | 0b0 – The system fan is not requested/off in Aux Power Mode. |
| 3306 | 0b1 – The system fan is requested/on in S5. | 3309 | 0b1 – The system fan is requested/on in Aux Power Mode. | |
| 3461 | The MAIN_PWR_EN pin is driven by the baseboard for normal operation in the S0 or S1 power state and may only be asserted when AUX_PWR_EN is already asserted. The MAIN_PWR_EN pin must be implemented on baseboard systems, but may optionally be used to control main power rail power supplies by the OCP NIC 3.0 card depending on the end point silicon implementation. Depending on the silicon vendor, end point devices may be able to operate in a single power domain, or may require separate power domains to function. | <> | 3464 | The MAIN_PWR_EN pin is driven by the baseboard for normal operation and may only be asserted when AUX_PWR_EN is already asserted. The MAIN_PWR_EN pin must be implemented on baseboard systems, but may optionally be used to control main power rail power supplies by the OCP NIC 3.0 card depending on the end point silicon implementation. Depending on the silicon vendor, end point devices may be able to operate in a single power domain, or may require separate power domains to function. |
| 3599 | MAIN_PWR_EN is asserted. An OP NIC 3.0 card is allowed a max ramp time TMPL between MAIN_PWR_EN assertion and NIC_PWR_GOOD reassertion. For cards that do not have a separate AUX and MAIN power domain, this state is an unconditional transition to NIC_PWR_GOOD. | <> | 3602 | MAIN_PWR_EN is asserted. An OP NIC 3.0 card is allowed a max ramp time TMPL between MAIN_PWR_EN assertion and NIC_PWR_GOOD reassertion. For cards that do not have a separate Aux and Main power domain, this state is an unconditional transition to NIC_PWR_GOOD. |
| 3777 | There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode (S5), and Main Power Mode (S0). These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 106 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.11. | <> | 3780 | There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode, and Main Power Mode. These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 106 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.11. |
| 3779 | <> | 3782 | ||
| 3811 | Aux Power Mode (S5) | <> | 3814 | Aux Power Mode |
| 3821 | Main Power Mode (S0) | <> | 3824 | Main Power Mode |
| 3841 | Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in ID Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 100 mV (TBD). The bleed resistor on the baseboard shall be 2.2 kΩ (TBD). If +12V_EDGE is present in ID Mode, the max usage is defined in Section 3.9. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0. | <> | 3844 | Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in ID Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max voltage leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 300 mV when a 1 kΩ bleed resistor is present on the baseboard. The baseboard bleed resistor is optional if the baseboard can tolerate leakage. If +12V_EDGE is present in ID Mode, the max usage is defined in Section 3.9. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0. |
| 3842 | Aux Power Mode (S5) | 3845 | Aux Power Mode | |
| 3843 | The Aux Power Mode provides both +3.3V_EDGE as well as +12V_EDGE is available. +12V_EDGE in Aux mode may be used to deliver power to the OCP NIC 3.0 card, but only up to the Aux mode budget as defined in Table 42. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=0, NIC_PWR_GOOD=1 and the duration (TAPL) has passed for the ID-Aux Power Mode ramp. This guarantees the ID mode to Aux Power Mode transition (as shown in Figure 107) has completed and all Aux Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met. | 3846 | The Aux Power Mode provides both +3.3V_EDGE as well as +12V_EDGE is available. +12V_EDGE in Aux mode may be used to deliver power to the OCP NIC 3.0 card, but only up to the Aux mode budget as defined in Table 42. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=0, NIC_PWR_GOOD=1 and the duration (TAPL) has passed for the ID-Aux Power Mode ramp. This guarantees the ID mode to Aux Power Mode transition (as shown in Figure 107) has completed and all Aux Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met. | |
| 3847 | For OCP NIC 3.0, Aux Power Mode corresponds to ACPI power state S5 on the system. This could also correspond to ACPI power state S3 or S4 depending on the implementation. | |||
| 3844 | Main Power Mode (S0) | 3848 | Main Power Mode | |
| -+ | 3850 | For OCP NIC 3.0, Main Power Mode corresponds to ACPI power state S0 on the system. This could also correspond to ACPI power state S1 depending on the implementation. | ||
| 3848 | Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in Programming Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 100 mV (TBD). The bleed resistor on the baseboard shall be 2.2 kΩ (TBD). If +12V_EDGE is present in Programming Mode, the max usage is defined in Section 3.9. | <> | 3853 | Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in Programming Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max voltage leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 300 mV when a 1 kΩ bleed resistor is present on the baseboard. The baseboard bleed resistor is optional if the baseboard can tolerate leakage. If +12V_EDGE is present in Programming Mode, the max usage is defined in Section 3.9. |
| 3867 | Aux Mode | <> | 3872 | Aux Power Mode |
| 3868 | Main Mode | 3873 | Main Power Mode | |
| 3906 | Aux Mode | <> | 3911 | Aux Power Mode |
| 3907 | Main Mode | 3912 | Main Power Mode | |
| -+ | 3968 | |||
| -+ | 3970 | |||
| -+ | 3972 | |||
| 4191 | The temperature reporting interface shall be accessible in Aux Power Mode (S5), and Main Power Mode (S0). Table 51 summarizes temperature reporting requirements. These requirements improve the system thermal management and allow the baseboard management device to access key component temperatures on an OCP NIC 3.0 card. When the temperature reporting function is implemented, it is required that the temperature reporting accuracy is within ±3 °C. | <> | 4199 | The temperature reporting interface shall be accessible in Aux Power Mode, and Main Power Mode. Table 51 summarizes temperature reporting requirements. These requirements improve the system thermal management and allow the baseboard management device to access key component temperatures on an OCP NIC 3.0 card. When the temperature reporting function is implemented, it is required that the temperature reporting accuracy is within ±3 °C. |
| 4269 | A pluggable transceiver module is a compact, hot-pluggable transceiver used to connect the OCP 3.0 NIC to an external physical medium. It is important for proper system operation to know the presence and temperature of pluggable transceiver modules. Table 53 summarizes pluggable module status reporting requirements. The transceiver temperature is always reported and is independent of the ASIC die temperature reporting requirements as discussed in Section 4.4. The temperature reporting interface shall be accessible in Aux Power Mode (S5), and Main Power Mode (S0). | <> | 4277 | A pluggable transceiver module is a compact, hot-pluggable transceiver used to connect the OCP 3.0 NIC to an external physical medium. It is important for proper system operation to know the presence and temperature of pluggable transceiver modules. Table 53 summarizes pluggable module status reporting requirements. The transceiver temperature is always reported and is independent of the ASIC die temperature reporting requirements as discussed in Section 4.4. The temperature reporting interface shall be accessible in Aux Power Mode, and Main Power Mode. |
| 4425 | The FRU EEPROM is readable in all four power states: ID mode, Programming mode, Aux Power mode (S5), and Main Power mode (S0). | <> | 4433 | The FRU EEPROM is readable in all four power states: ID mode, Programming mode, Aux Power Mode, and Main Power Mode. |
| 4453 | Card Max power (in Watts) in MAIN (S0) mode. | <> | 4461 | Card Max power (in Watts) in Main Power Mode. |
| 4454 | The encoded value is the calculated max power of the OCP NIC 3.0 card in the Main Power (S0) mode only and does not include the consumed power by transceivers plugged into the line side receptacle(s). | 4462 | The encoded value is the calculated max power of the OCP NIC 3.0 card in the Main Power Mode only and does not include the consumed power by transceivers plugged into the line side receptacle(s). | |
| 4458 | Card Max power (in Watts) in AUX (S5) mode. | <> | 4466 | Card Max power (in Watts) in Aux Power Mode. |
| 4459 | The encoded value is the calculated max power of the OCP NIC 3.0 card in the Aux Power (S5) mode only and does not include the consumed power by transceivers plugged into the line side receptacle(s). | 4467 | The encoded value is the calculated max power of the OCP NIC 3.0 card in the Aux Power Mode only and does not include the consumed power by transceivers plugged into the line side receptacle(s). | |
| 4479 | The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with active cables while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements. | <> | 4487 | The encoded value represents the amount of airflow, in LFM, required to cool the card in Aux Power Mode with active cables while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
| 4481 | 0x0000-0xFFFE – LFM required for cooling card in Hot Aisle Operation.0xFFFF – Unknown. | <> | 4489 | 0x0000 – Card only supports passive cables (e.g., RJ45)0x0001 – 0xFFFE – LFM required for cooling card in Hot Aisle Operation.0xFFFF – Unknown. |
| 4485 | The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with active cables while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements. | <> | 4493 | The encoded value represents the amount of airflow, in LFM, required to cool the card in Aux Power Mode with active cables while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
| 4487 | 0x0000-0xFFFE – LFM required for cooling card in Cold Aisle Operation.0xFFFF – Unknown. | <> | 4495 | 0x0000 – Card only supports passive cables (e.g., RJ45)0x0001 – 0xFFFE – LFM required for cooling card in Cold Aisle Operation.0xFFFF – Unknown. |
| 4556 | The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with passive cables or RJ45 while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements. | <> | 4564 | The encoded value represents the amount of airflow, in LFM, required to cool the card in Aux Power Mode with passive cables or RJ45 while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
| 4562 | The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with passive cables or RJ45 while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements. | <> | 4570 | The encoded value represents the amount of airflow, in LFM, required to cool the card in Aux Power Mode with passive cables or RJ45 while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
| 4861 | It is important to point out that the curves shown in Figure 120 represent only the maximum ASIC power that can be supported vs. the supplied inlet velocity. Other heat loads on the card may require airflow velocities above and beyond that required to cool the ASIC. SFP or QSFP optical transceivers located downstream of the AISC will in many cases pose a greater cooling challenge than the ASIC cooling. Cooling the optical transceivers becomes even more difficult as the ASIC power is increased due to additional preheating of the air as it moves through the ASIC heatsink. OCP NIC 3.0 designers must consider all heat sources early in the design process to ensure the card thermal solution is sufficient for the feature set. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. | <> | 4869 | It is important to point out that the curves shown in Figure 120 represent only the maximum ASIC power that can be supported vs. the supplied inlet velocity. Other heat loads on the card may require airflow velocities above and beyond that required to cool the ASIC. SFP or QSFP optical transceivers located downstream of the AISC will in many cases pose a greater cooling challenge than the ASIC cooling. Cooling the optical transceivers becomes even more difficult as the ASIC power is increased due to additional preheating of the air as it moves through the ASIC heatsink. OCP NIC 3.0 designers must consider all heat sources early in the design process to ensure the card thermal solution is sufficient for the feature set. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. |
| 4864 | The server airflow capability is typically more restrictive when the OCP card is operating in standby mode (S5). The airflow available from the system cooling solution is often more restrictive due to limited power budget available in an S5 state. The graph below emphasizes that though the local OCP NIC 3.0 air temperature is typically lower than in S0 (since preheating from upstream components should be greatly reduced while in standby), the upper bound of local air velocity is a fraction of what can be generated when the system is in main power mode (S0). Card vendors must test for these conditions, making sure that the provided cooling is sufficient for both the ASIC and any installed transceivers (which will still be receiving preheat from the ASIC in S5 mode). | <> | 4872 | The server airflow capability is typically more restrictive when the OCP card is operating in Aux Power Mode. The airflow available from the system cooling solution is often more restrictive due to limited power budget available in Aux Power Mode. The graph below emphasizes that though the local OCP NIC 3.0 air temperature is typically lower in Main Power Mode (since preheating from upstream components should be greatly reduced while in standby), the upper bound of local air velocity is a fraction of what can be generated when the system is in Main Power Mode. Card vendors must test for these conditions, making sure that the provided cooling is sufficient for both the ASIC and any installed transceivers (which will still be receiving preheat from the ASIC in Aux Power Mode). |
| 4865 | The NIC vendor shall provide the required LFM during S5 state in the FRU EEPROM (see Section 4.10.3). The cold aisle should be tested at 35 °C; the hot aisle should be tested at 45 °C. | 4873 | The NIC vendor shall provide the required LFM during for Aux Power Mode in the FRU EEPROM (see Section 4.10.3). The cold aisle should be tested at 35 °C; the hot aisle should be tested at 45 °C. | |
| 4866 | Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode | 4874 | Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in Aux Power Mode | |
| 4905 | It is important to note that the supportable power for the LFF card is considerably higher than for the SFF card due to the increased size of the ASIC heatsink. In addition, optics module cooling on the LFF card will also be considerably improved due to the arrangement of the optics in parallel to the ASIC heatsink rather than in series. These thermal advantages are key drivers for the LFF card geometry. The OCP NIC 3.0 simulation was conducted within a virtual version of the LFF card test fixture defined in Section 6.4. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. | <> | 4913 | It is important to note that the supportable power for the LFF card is considerably higher than for the SFF card due to the increased size of the ASIC heatsink. In addition, optics module cooling on the LFF card will also be considerably improved due to the arrangement of the optics in parallel to the ASIC heatsink rather than in series. These thermal advantages are key drivers for the LFF card geometry. The OCP NIC 3.0 simulation was conducted within a virtual version of the LFF card test fixture defined in Section 6.4. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. |
| 4913 | Similar to Figure 122 for Hot Aisle cooling, Figure 128 below shows the ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling. | <> | 4921 | Similar to Figure 122 for Hot Aisle cooling, Figure 128 below shows the ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling. |
| 4920 | Similar to Figure 128 for LFF Hot Aisle cooling, Figure 131 below shows the LFF ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling. | <> | 4928 | Similar to Figure 128 for LFF Hot Aisle cooling, Figure 131 below shows the LFF ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling. |
| 5131 | - Change NC-SI over RBT RXD/TXD pins to a pull-up instead of a pull down.- Update power sequencing diagram. REFCLK is disabled before silicon transitions to AUX Power Mode. | <> | 5139 | - Change NC-SI over RBT RXD/TXD pins to a pull-up instead of a pull down.- Update power sequencing diagram. REFCLK is disabled before silicon transitions to Aux Power Mode. |
| 5171 | - Section 3.9.x – Clarified ID-Aux and Aux-Main Power Mode transition requirements to prevent sampling health status pins until cards have fully entered into Aux and Main modes to prevent false indication. | <> | 5179 | - Section 3.9.x – Clarified ID-Aux and Aux-Main Power Mode transition requirements to prevent sampling health status pins until cards have fully entered into Aux and Main Power Modes to prevent false indication. |
| 5246 | - Sections 6.2.x – Add notes to consider airflow requirements in Aux and Main power modes for SFF & LFF in Hot & Cold Aisle implementations. | <> | 5254 | - Sections 6.2.x – Add notes to consider airflow requirements in Aux and Main Power Modes for SFF & LFF in Hot & Cold Aisle implementations. |
| -+ | 5338 | - General – Uniformly changed references for Aux Power Mode and Main Power Mode. Removed references to ACPI power states S5 and S0. Added additional text to Section 3.8.3 and 3.8.4 for the included ACPI power states. | ||
| <> | 5342 | - Section 2.5.1, 2.5.2 – Figure 24 & 29 - Update PCB break off note #3 to include feature max tolerances.- Section 2.8.2 – Figure 40 – Updated dimension notation with parenthesis and add center line labeled as CL DATUM H for consistency across form-factor figures. | ||
| 5333 | - Section 2.5.1, 2.5.2 – Update PCB break off note #3 to include feature max tolerances. | 5343 | - Section 2.8.3 – Figure 43 – Add center line labeled as CL DATUM H for consistency across form-factor figures. | |
| 5344 | - Section 2.8.4 – Figure 46 – Add center line labeled as CL DATUM H for consistency across form-factor figures. | |||
| 5345 | - Section 3. 4 – Add clarification statement for Aux Power Mode and Main Power Mode in relation to ACPI power states. | |||
| <> | 5350 | - Section 3.8.3 – Clarified that Aux Power Mode includes ACPI power states S3, S4 and S5 as they are equivalent from a power delivery and sequencing perspective. | ||
| 5338 | - Section 3.8.2, 3.8.5 – Clarifications to +12V_EDGE in ID/Programming mode. +12V_EDGE is now marked as optional in these two states. A max permissible leakage voltage is stated and the baseboard requires a bleed resistor. | 5351 | - Section 3.8.2, 3.8.5 – Clarifications to +12V_EDGE in ID/Programming mode. +12V_EDGE is now marked as optional in these two states. A max permissible leakage voltage is stated and the baseboard has an optional a bleed resistor. | |
| 5345 | Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. | <> | 5358 | Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19. |
| 5346 | Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. | 5359 | Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19. | |
| -+ | 5367 | OCP NIC 3.0 Subgroup | ||
| 5368 | Document release - version R1.1.0 | |||
| 5369 | 1.1.0 | |||
| 5370 | 10/xx/2020 | |||
| 5363 | - Offset 4, 5 – Clarified that the Card Max Power in Main mode and the Card Max Power in Aux Mode do not include the power consumed by transceivers plugged into the line side receptacle(s). | <> | 5380 | - Offset 4, 5 – Clarified that the Card Max Power in Main Power Mode and the Card Max Power in Aux Power Mode do not include the power consumed by transceivers plugged into the line side receptacle(s). |
| 5407 | - Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. | <> | 5424 | - Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19. |
| 5408 | - Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. | 5425 | - Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19. | |