| 107 | 3.10.1 Power Sequence Timing Requirements 150 | <> | 107 | 3.11 Power Sequence Timing Requirements 150 |
| 108 | 3.11 Digital I/O Specifications 154 | 108 | 3.12 Digital I/O Specifications 154 | |
| 115 | 4.6 Pluggable Transceiver Module Status and Temperature Reporting 161 | <> | 115 | 4.6 Pluggable Transceiver Module Status and Temperature Reporting 162 |
| 267 | Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[0:2]#) 95 | <> | 267 | Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[2:0]#) 95 |
| 268 | Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[0:2]#) 95 | 268 | Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[2:0]#) 95 | |
| 274 | Figure 88: Scan Chain Connection Example 113 | <> | 274 | Figure 89: Scan Chain Connection Example 113 |
| 275 | Figure 89: Example Power Supply Topology 118 | 275 | Figure 90: Example Power Supply Topology 118 | |
| 276 | Figure 90: USB 2.0 Connection Example – Basic Connectivity 120 | 276 | Figure 91: USB 2.0 Connection Example – Basic Connectivity 120 | |
| 277 | Figure 91: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity 120 | 277 | Figure 92: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity 120 | |
| 278 | Figure 92: UART Connection Example 122 | 278 | Figure 93: UART Connection Example 122 | |
| 279 | Figure 93: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller) 128 | 279 | Figure 94: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller) 128 | |
| 280 | Figure 94: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers) 129 | 280 | Figure 95: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers) 129 | |
| 281 | Figure 95: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller) 130 | 281 | Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller) 130 | |
| 282 | Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers) 131 | 282 | Figure 97: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers) 131 | |
| 283 | Figure 97: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers) 132 | 283 | Figure 98: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers) 132 | |
| 284 | Figure 98: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links 134 | 284 | Figure 99: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links 134 | |
| 285 | Figure 99: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links 135 | 285 | Figure 100: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links 135 | |
| 286 | Figure 100: SFF PCIe REFCLK Mapping – Quad Host – 4 Links 136 | 286 | Figure 101: SFF PCIe REFCLK Mapping – Quad Host – 4 Links 136 | |
| 287 | Figure 101: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links 137 | 287 | Figure 102: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links 137 | |
| 288 | Figure 102: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links 138 | 288 | Figure 103: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links 138 | |
| 289 | Figure 103: LFF PCIe REFCLK Mapping – Quad Host – 4 Links 139 | 289 | Figure 104: LFF PCIe REFCLK Mapping – Quad Host – 4 Links 139 | |
| 290 | Figure 104: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement 143 | 290 | Figure 105: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement 143 | |
| 291 | Figure 105: Baseboard Power States 145 | 291 | Figure 106: Baseboard Power States 145 | |
| 292 | Figure 106: Power-Up Sequencing – Normal Operation 150 | 292 | Figure 107: Power-Up Sequencing – Normal Operation 150 | |
| 293 | Figure 107: Power-Down Sequencing – Normal Operation 151 | 293 | Figure 108: Power-Down Sequencing – Normal Operation 151 | |
| 294 | Figure 108: Programming Mode Sequencing 152 | 294 | Figure 109: Programming Mode Sequencing 152 | |
| 295 | Figure 109: FRU EEPROM Writes with Double Byte Addressing 166 | 295 | Figure 110: FRU EEPROM Writes with Double Byte Addressing 166 | |
| 296 | Figure 110: FRU EEPROM Reads with Double Byte Addressing 166 | 296 | Figure 111: FRU EEPROM Reads with Double Byte Addressing 166 | |
| 297 | Figure 111: FRU Update Flow 167 | 297 | Figure 112: FRU Update Flow 167 | |
| 298 | Figure 112: NC-SI over RBT Timing Budget Topology 175 | 298 | Figure 113: NC-SI over RBT Timing Budget Topology 175 | |
| 299 | Figure 113: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer 178 | 299 | Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer 178 | |
| 300 | Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer 178 | 300 | Figure 115: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer 178 | |
| 301 | Figure 115: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF 180 | 301 | Figure 116: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF 180 | |
| 302 | Figure 116: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF 182 | 302 | Figure 117: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF 182 | |
| 303 | Figure 117: Airflow Direction for Hot Aisle Cooling (SFF and LFF) 184 | 303 | Figure 118: Airflow Direction for Hot Aisle Cooling (SFF and LFF) 184 | |
| 304 | Figure 118: Airflow Direction for Cold Aisle Cooling (SFF and LFF) 185 | 304 | Figure 119: Airflow Direction for Cold Aisle Cooling (SFF and LFF) 185 | |
| 305 | Figure 119: ASIC Supportable Power for Hot Aisle Cooling – SFF 186 | 305 | Figure 120: ASIC Supportable Power for Hot Aisle Cooling – SFF 186 | |
| 306 | Figure 120: OCP NIC 3.0 SFF Reference Design and CFD Geometry 187 | 306 | Figure 121: OCP NIC 3.0 SFF Reference Design and CFD Geometry 187 | |
| 307 | Figure 121: Server System Airflow Capability – SFF Card Hot Aisle Cooling 188 | 307 | Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling 188 | |
| 308 | Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode 189 | 308 | Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode 189 | |
| 309 | Figure 123: ASIC Supportable Power for Hot Aisle Cooling – LFF Card 190 | 309 | Figure 124: ASIC Supportable Power for Hot Aisle Cooling – LFF Card 190 | |
| 310 | Figure 124: OCP NIC 3.0 LFF Reference Design and CFD Geometry 190 | 310 | Figure 125: OCP NIC 3.0 LFF Reference Design and CFD Geometry 190 | |
| 311 | Figure 125: Server System Airflow Capability – LFF Card Hot Aisle Cooling 192 | 311 | Figure 126: Server System Airflow Capability – LFF Card Hot Aisle Cooling 192 | |
| 312 | Figure 126: ASIC Supportable Power for Cold Aisle Cooling – SFF Card 193 | 312 | Figure 127: ASIC Supportable Power for Cold Aisle Cooling – SFF Card 193 | |
| 313 | Figure 127: Server System Airflow Capability – SFF Cold Aisle Cooling 194 | 313 | Figure 128: Server System Airflow Capability – SFF Cold Aisle Cooling 194 | |
| 314 | Figure 128: ASIC Supportable Power Comparison – SFF Card 194 | 314 | Figure 129: ASIC Supportable Power Comparison – SFF Card 194 | |
| 315 | Figure 129: ASIC Supportable Power for Cold Aisle Cooling – LFF Card 195 | 315 | Figure 130: ASIC Supportable Power for Cold Aisle Cooling – LFF Card 195 | |
| 316 | Figure 130: Server System Airflow Capability – LFF Cold Aisle Cooling 196 | 316 | Figure 131: Server System Airflow Capability – LFF Cold Aisle Cooling 196 | |
| 317 | Figure 131: ASIC Supportable Power Comparison – LFF Card 196 | 317 | Figure 132: ASIC Supportable Power Comparison – LFF Card 196 | |
| 318 | Figure 132: SFF Thermal Test Fixture Preliminary Design 198 | 318 | Figure 133: SFF Thermal Test Fixture Preliminary Design 198 | |
| 319 | Figure 133: SFF Thermal Test Fixture Preliminary Design – Cover Removed 199 | 319 | Figure 134: SFF Thermal Test Fixture Preliminary Design – Cover Removed 199 | |
| 320 | Figure 134: SFF Card Thermal Test Fixture PCB 199 | 320 | Figure 135: SFF Card Thermal Test Fixture PCB 199 | |
| 321 | Figure 135: LFF Card Thermal Test Fixture Design 200 | 321 | Figure 136: LFF Card Thermal Test Fixture Design 200 | |
| 322 | Figure 136: LFF Card Thermal Test Fixture Design – Cover Removed 200 | 322 | Figure 137: LFF Card Thermal Test Fixture Design – Cover Removed 200 | |
| 323 | Figure 137: LFF Card Thermal Test Fixture PCB 201 | 323 | Figure 138: LFF Card Thermal Test Fixture PCB 201 | |
| 324 | Figure 138: Thermal Test Fixture Airflow Direction 202 | 324 | Figure 139: Thermal Test Fixture Airflow Direction 202 | |
| 325 | Figure 139: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 203 | 325 | Figure 140: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 203 | |
| 326 | Figure 140: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 203 | 326 | Figure 141: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 203 | |
| 327 | Figure 141: Graphical View of Card Cooling Tiers 205 | 327 | Figure 142: Graphical View of Card Cooling Tiers 205 | |
| 328 | Figure 142: Typical Operating Range for Hot Aisle Configurations 205 | 328 | Figure 143: Typical Operating Range for Hot Aisle Configurations 205 | |
| 329 | Figure 143: Typical Operating Range for Cold Aisle Configurations 206 | 329 | Figure 144: Typical Operating Range for Cold Aisle Configurations 206 | |
| 330 | Figure 144: SFF Shock and Vibe Fixture 207 | 330 | Figure 145: SFF Shock and Vibe Fixture 207 | |
| 331 | Figure 145: LFF Shock and Vibe Fixture 207 | 331 | Figure 146: LFF Shock and Vibe Fixture 207 | |
| 332 | Figure 146: Dye and Pull Type Locations 210 | 332 | Figure 147: Dye and Pull Type Locations 210 | |
| 333 | Figure 147: Dye Coverage Percentage 210 | 333 | Figure 148: Dye Coverage Percentage 210 | |
| 336 | Table 3: Acronyms 14 | <> | 336 | Table 2: Acronyms 14 |
| 337 | Table 4: OCP 3.0 Form Factor Dimensions 19 | 337 | Table 3: OCP 3.0 Form Factor Dimensions 19 | |
| 338 | Table 5: Baseboard to OCP NIC Form Factor Compatibility Chart 19 | 338 | Table 4: Baseboard to OCP NIC Form Factor Compatibility Chart 19 | |
| 339 | Table 6: Example Non-NIC Use Cases 21 | 339 | Table 5: Example Non-NIC Use Cases 21 | |
| 340 | Table 7: OCP NIC 3.0 Card Definitions 25 | 340 | Table 6: OCP NIC 3.0 Card Definitions 25 | |
| 341 | Table 8: OCP NIC 3.0 Line Side I/O Implementations 33 | 341 | Table 7: OCP NIC 3.0 Line Side I/O Implementations 33 | |
| 342 | Table 9: Line Side I/O Cross Reference to Industry Standards 33 | 342 | Table 8: Line Side I/O Cross Reference to Industry Standards 33 | |
| 343 | Table 10: Bill of Materials for the SFF and LFF Faceplate Assemblies 36 | 343 | Table 9: Bill of Materials for the SFF and LFF Faceplate Assemblies 36 | |
| 344 | Table 11: CTF Default Tolerances (SFF and LFF OCP NIC 3.0) 56 | 344 | Table 10: CTF Default Tolerances (SFF and LFF OCP NIC 3.0) 56 | |
| 345 | Table 12: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller 69 | 345 | Table 11: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller 69 | |
| 346 | Table 13: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller 69 | 346 | Table 12: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller 69 | |
| 347 | Table 14: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controller 70 | 347 | Table 13: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controller 70 | |
| 348 | Table 15: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller 71 | 348 | Table 14: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller 71 | |
| 349 | Table 16: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller 71 | 349 | Table 15: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller 71 | |
| 350 | Table 17: NIC Implementation Examples and 3D CAD 72 | 350 | Table 16: NIC Implementation Examples and 3D CAD 72 | |
| 351 | Table 18: Contact Mating Positions for the Primary Connector 75 | 351 | Table 17: Contact Mating Positions for the Primary Connector 75 | |
| 352 | Table 19: Contact Mating Positions for the Secondary Connector 77 | 352 | Table 18: Contact Mating Positions for the Secondary Connector 77 | |
| 353 | Table 20: Right Angle Connector Options 79 | 353 | Table 19: Right Angle Connector Options 79 | |
| 354 | Table 21: Straddle Mount Connector Options 80 | 354 | Table 20: Straddle Mount Connector Options 80 | |
| 355 | Table 22: Primary Connector Pin Definition (x16) (4C+) 84 | 355 | Table 21: Primary Connector Pin Definition (x16) (4C+) 84 | |
| 356 | Table 23: Secondary Connector Pin Definition (x16) (4C) 86 | 356 | Table 22: Secondary Connector Pin Definition (x16) (4C) 86 | |
| 357 | Table 24: Pin Descriptions – PCIe 87 | 357 | Table 23: Pin Descriptions – PCIe 87 | |
| 358 | Table 25: Pin Descriptions – PCIe Present and Bifurcation Control Pins 93 | 358 | Table 24: Pin Descriptions – PCIe Present and Bifurcation Control Pins 93 | |
| 359 | Table 26: Pin Descriptions – SMBus 96 | 359 | Table 25: Pin Descriptions – SMBus 96 | |
| 360 | Table 27: Pin Descriptions – NC-SI over RBT 97 | 360 | Table 26: Pin Descriptions – NC-SI over RBT 97 | |
| 361 | Table 28: Pin Descriptions – Scan Chain 105 | 361 | Table 27: Pin Descriptions – Scan Chain 105 | |
| 362 | Table 29: Scan Chain Timing Requirements – Baseboard Side 107 | 362 | Table 28: Scan Chain Timing Requirements – Baseboard Side 107 | |
| 363 | Table 30: Scan Chain Timing Requirements – OCP NIC 3.0 Card Side 107 | 363 | Table 29: Scan Chain Timing Requirements – OCP NIC 3.0 Card Side 107 | |
| 364 | Table 31: Pin Descriptions – Scan Chain DATA_OUT Bit Definition 108 | 364 | Table 30: Pin Descriptions – Scan Chain DATA_OUT Bit Definition 108 | |
| 365 | Table 32: Pin Descriptions – Scan Chain DATA_IN Bit Definition 108 | 365 | Table 31: Pin Descriptions – Scan Chain DATA_IN Bit Definition 108 | |
| 366 | Table 33: Pin Descriptions – Power 114 | 366 | Table 32: Pin Descriptions – Power 114 | |
| 367 | Table 34: Pin Descriptions – USB 2.0 – Primary Connector only 119 | 367 | Table 33: Pin Descriptions – USB 2.0 – Primary Connector only 119 | |
| 368 | Table 35: Pin Descriptions – UART – Secondary Connector Only 121 | 368 | Table 34: Pin Descriptions – UART – Secondary Connector Only 121 | |
| 369 | Table 36: Pin Descriptions – RFU[1:4] 123 | 369 | Table 35: Pin Descriptions – RFU[1:4] 123 | |
| 370 | Table 37: PCIe Bifurcation Decoder for x32, x16, x8, x4, x2 and x1 Card Widths 126 | 370 | Table 36: PCIe Bifurcation Decoder for x32, x16, x8, x4, x2 and x1 Card Widths 126 | |
| 371 | Table 38: PCIe REFCLK and PERST Associations 133 | 371 | Table 37: PCIe REFCLK and PERST Associations 133 | |
| 372 | Table 39: SFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links 133 | 372 | Table 38: SFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links 133 | |
| 373 | Table 40: LFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2, 4 and 8 Links 133 | 373 | Table 39: LFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2, 4 and 8 Links 133 | |
| 374 | Table 41: OCP NIC 3.0 Card LED Configuration with Two Physical LEDs per Port 141 | 374 | Table 40: OCP NIC 3.0 Card LED Configuration with Two Physical LEDs per Port 141 | |
| 375 | Table 42: Available Card Functions per Power State 146 | 375 | Table 41: Available Card Functions per Power State 146 | |
| 376 | Table 43: Baseboard Power Supply Rail Requirements – Slot Power Envelopes 148 | 376 | Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes 148 | |
| 377 | Table 44: Power Sequencing Parameters 152 | 377 | Table 43: Power Sequencing Parameters 152 | |
| 378 | Table 45: Digital I/O DC specifications 154 | 378 | Table 44: Digital I/O DC specifications 154 | |
| 379 | Table 46: Digital I/O AC specifications 154 | 379 | Table 45: Digital I/O AC specifications 154 | |
| 380 | Table 47: OCP NIC 3.0 Management Implementation Definitions 155 | 380 | Table 46: OCP NIC 3.0 Management Implementation Definitions 155 | |
| 381 | Table 48: Sideband Management Interface and Transport Requirements 155 | 381 | Table 47: Sideband Management Interface and Transport Requirements 155 | |
| 382 | Table 49: NC-SI Traffic Requirements 156 | 382 | Table 48: NC-SI Traffic Requirements 156 | |
| 383 | Table 50: MC MAC Address Provisioning Requirements 156 | 383 | Table 49: MC MAC Address Provisioning Requirements 156 | |
| 384 | Table 51: Threshold Severity Level vs Example Threshold Values 159 | 384 | Table 50: Threshold Severity Level vs Example Threshold Values 159 | |
| 385 | Table 52: Temperature Reporting Requirements 159 | 385 | Table 51: Temperature Reporting Requirements 159 | |
| 386 | Table 53: Power Consumption Reporting Requirements 161 | 386 | Table 52: Power Consumption Reporting Requirements 161 | |
| 387 | Table 54: Pluggable Module Status Reporting Requirements 162 | 387 | Table 53: Pluggable Module Status Reporting Requirements 162 | |
| 388 | Table 55: Management and Pre-OS Firmware Inventory and Update Requirements 162 | 388 | Table 54: Management and Pre-OS Firmware Inventory and Update Requirements 162 | |
| 389 | Table 56: Slot_ID[1:0] to Package ID[2:0] Mapping 164 | 389 | Table 55: Slot_ID[1:0] to Package ID[2:0] Mapping 164 | |
| 390 | Table 57: FRU EEPROM Address Map 165 | 390 | Table 56: FRU EEPROM Address Map 165 | |
| 391 | Table 58: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00 168 | 391 | Table 57: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00 168 | |
| 392 | Table 59: NC-SI over RBT Timing Parameters 175 | 392 | Table 58: NC-SI over RBT Timing Parameters 175 | |
| 393 | Table 60: PCIe Electrical Budgets 179 | 393 | Table 59: PCIe Electrical Budgets 179 | |
| 394 | Table 61: PCIe Test Fixtures for OCP NIC 3.0 180 | 394 | Table 60: PCIe Test Fixtures for OCP NIC 3.0 180 | |
| 395 | Table 62: Hot Aisle Air Temperature Boundary Conditions 185 | 395 | Table 61: Hot Aisle Air Temperature Boundary Conditions 185 | |
| 396 | Table 63: Hot Aisle Airflow Boundary Conditions 185 | 396 | Table 62: Hot Aisle Airflow Boundary Conditions 185 | |
| 397 | Table 64: Cold Aisle Air Temperature Boundary Conditions 185 | 397 | Table 63: Cold Aisle Air Temperature Boundary Conditions 185 | |
| 398 | Table 65: Cold Aisle Airflow Boundary Conditions 186 | 398 | Table 64: Cold Aisle Airflow Boundary Conditions 186 | |
| 399 | Table 66: Reference OCP NIC 3.0 SFF Card Geometry 187 | 399 | Table 65: Reference OCP NIC 3.0 SFF Card Geometry 187 | |
| 400 | Table 67: Reference OCP NIC 3.0 LFF Card Geometry 191 | 400 | Table 66: Reference OCP NIC 3.0 LFF Card Geometry 191 | |
| 401 | Table 68: Card Cooling Tier Definitions (LFM) 204 | 401 | Table 67: Card Cooling Tier Definitions (LFM) 204 | |
| 402 | Table 69: Random Vibration Testing 1.88 GRMS Profile 208 | 402 | Table 68: Random Vibration Testing 1.88 GRMS Profile 208 | |
| 403 | Table 70: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location 212 | 403 | Table 69: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location 212 | |
| 404 | Table 71: Safety Requirements 213 | 404 | Table 70: Safety Requirements 213 | |
| 405 | Table 72: Immunity (ESD) Requirements 213 | 405 | Table 71: Immunity (ESD) Requirements 213 | |
| 424 | NVIDIA Mellanox Networking | <> | 424 | NVIDIA |
| -+ | 446 | DMTF Standard. DSP2054, PLDM NIC Modeling. Distributed Management Task Force (DMTF), Rev 1.0.0, December 18th, 2019. | ||
| 2975 | This section provides the pin assignments for the PCIe present and bifurcation control signals. The AC/DC specifications are defined in Section 3.10.1. Example connection diagrams are shown in Figure 82 and Figure 83. | <> | 2976 | This section provides the pin assignments for the PCIe present and bifurcation control signals. The AC/DC specifications are defined in Section 3.11. Example connection diagrams are shown in Figure 82 and Figure 83. |
| 2976 | The PRSNTA#/PRSNTB[0:3]# state shall be used to determine if a card has been physically plugged in. The BIF[0:2]# pins shall be asserted by the baseboard along with the rising edge of AUX_PWR_EN. The BIF[0:2]# pins shall be latched by the OCP NIC 3.0 card when AUX_PWR_EN=1 and NIC_PWR_GOOD=1 to ensure the correct values are detected by the OCP NIC 3.0 card. Changing the pin states after this timing window is not allowed. Refer to the AC timing diagram in Section 3.10.1 for details. | 2977 | The PRSNTA#/PRSNTB[3:0]# state shall be used to determine if a card has been physically plugged in. The BIF[2:0]# pins shall be asserted by the baseboard along with the rising edge of AUX_PWR_EN. The BIF[2:0]# pins shall be latched by the OCP NIC 3.0 card when AUX_PWR_EN=1 and NIC_PWR_GOOD=1 to ensure the correct values are detected by the OCP NIC 3.0 card. Changing the pin states after this timing window is not allowed. Refer to the AC timing diagram in Section 3.11 for details. | |
| 2977 | PRSNTB[0:3]# pins are available to each connector and are independent of each other. For the SFF, the baseboard shall only read the Primary Connector PRSNTB[0:3]# to determine the card type. For the LFF, the baseboard shall read both the Primary and Secondary connector PRSNTB[0:3]# pins to determine the card type. The card type matrix is discussed in Section 3.5. | 2978 | PRSNTB[3:0]# pins are available to each connector and are independent of each other. For the SFF, the baseboard shall only read the Primary Connector PRSNTB[3:0]# to determine the card type. For the LFF, the baseboard shall read both the Primary and Secondary connector PRSNTB[3:0]# pins to determine the card type. The card type matrix is discussed in Section 3.5. | |
| 2998 | Present B [0:3]# are used for OCP NIC 3.0 card presence and PCIe capabilities detection. | <> | 2999 | Present B [3:0]# are used for OCP NIC 3.0 card presence and PCIe capabilities detection. |
| 3009 | Bifurcation [0:2]# pins allow the baseboard to force configure the OCP NIC 3.0 card bifurcation. | <> | 3010 | Bifurcation [2:0]# pins allow the baseboard to force configure the OCP NIC 3.0 card bifurcation. |
| 3010 | For baseboards, the BIF[0:2]# pins shall be driven from the baseboard I/O hub on the rising edge of AUX_PWR_EN. This allows the baseboard to force the OCP NIC 3.0 card bifurcation. The baseboard may optionally pull the BIF[0:2]# signals to AUX_PWR_EN or to ground per the definitions described in Section 3.5 if no dynamic bifurcation configuration is required. The BIF[0:2]# pins shall be low until AUX_PWR_EN is asserted. | 3011 | For baseboards, the BIF[2:0]# pins shall be driven from the baseboard I/O hub on the rising edge of AUX_PWR_EN. This allows the baseboard to force the OCP NIC 3.0 card bifurcation. The baseboard may optionally pull the BIF[2:0]# signals to AUX_PWR_EN or to ground per the definitions described in Section 3.5 if no dynamic bifurcation configuration is required. The BIF[2:0]# pins shall be low until AUX_PWR_EN is asserted. | |
| 3011 | For baseboards that allow dynamic bifurcation, the BIF[0:2] pins are driven low prior to AUX_PWR_EN. The state of the BIF[0:2] pins are driven with the rising edge of AUX_PWR_EN when bifurcation is requested. Refer to Figure 82 for an example configuration. | 3012 | For baseboards that allow dynamic bifurcation, the BIF[2:0] pins are driven low prior to AUX_PWR_EN. The state of the BIF[2:0] pins are driven with the rising edge of AUX_PWR_EN when bifurcation is requested. Refer to Figure 82 for an example configuration. | |
| 3013 | For OCP NIC 3.0 cards, these signals shall connect to the endpoint bifurcation pins if it is supported. The BIF[0:2]# signals shall be left as no connects if end point bifurcation is not supported. The value of the BIF[2:0]# pins are latched by the OCP NIC 3.0 card upon entering the AUX power mode state (when AUX_PWR_EN=1 and NIC_PWR_GOOD=1). | <> | 3014 | For OCP NIC 3.0 cards, these signals shall connect to the endpoint bifurcation pins if it is supported. The BIF[2:0]# signals shall be left as no connects if end point bifurcation is not supported. The value of the BIF[2:0]# pins are latched by the OCP NIC 3.0 card upon entering the AUX power mode state (when AUX_PWR_EN=1 and NIC_PWR_GOOD=1). |
| 3015 | Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[0:2]#) | <> | 3016 | Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[2:0]#) |
| 3016 | Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[0:2]#) | 3017 | Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[2:0]#) | |
| 3251 | The Scan Chain DATA_IN bus is an input to the host and provides NIC status indication. The default implementation is completed with two 8-bit 74LV165 parallel into serial out shift registers in a cascaded implementation. Up to four shift registers may be implemented to provide additional NIC status indication to the host platform. Alternatively, an OCP NIC 3.0 card vendor may choose to implement this chain using an active device (such as a microcontroller or CPLD), as long as it implements the function of the 74LV165, supporting circuitry for the Scan Chain and meets all of the timing specifications given in this specification. For active device implementations, there is an associated device start-up time. Refer to Section 3.10.1 for details on the +3.3V_EDGE stable to the first data valid read in ID Mode. | <> | 3252 | The Scan Chain DATA_IN bus is an input to the host and provides NIC status indication. The default implementation is completed with two 8-bit 74LV165 parallel into serial out shift registers in a cascaded implementation. Up to four shift registers may be implemented to provide additional NIC status indication to the host platform. Alternatively, an OCP NIC 3.0 card vendor may choose to implement this chain using an active device (such as a microcontroller or CPLD), as long as it implements the function of the 74LV165, supporting circuitry for the Scan Chain and meets all of the timing specifications given in this specification. For active device implementations, there is an associated device start-up time. Refer to Section 3.11 for details on the +3.3V_EDGE stable to the first data valid read in ID Mode. |
| 3460 | The MAIN_PWR_EN pin is driven by the baseboard and may only be asserted when AUX_PWR_EN is already asserted for normal operation in the S0 power state. The MAIN_PWR_EN pin must be implemented on baseboard systems, but may optionally be used to control main power rail power supplies by the OCP NIC 3.0 card depending on the end point silicon implementation. Depending on the silicon vendor, end point devices may be able to operate in a single power domain, or may require separate power domains to function. | <> | 3461 | The MAIN_PWR_EN pin is driven by the baseboard for normal operation in the S0 or S1 power state and may only be asserted when AUX_PWR_EN is already asserted. The MAIN_PWR_EN pin must be implemented on baseboard systems, but may optionally be used to control main power rail power supplies by the OCP NIC 3.0 card depending on the end point silicon implementation. Depending on the silicon vendor, end point devices may be able to operate in a single power domain, or may require separate power domains to function. |
| 3479 | Yes | <> | 3480 | N/A |
| 3489 | Yes | <> | 3490 | N/A |
| 3497 | 0 | +- | ||
| 3498 | 0 | |||
| 3499 | No | |||
| 3500 | 0 | |||
| 3501 | ID Mode | |||
| 3506 | Aux Power Mode | <> | 3502 | Transition state (non-operational) |
| 3507 | 0 | |||
| 3509 | No | +- | ||
| 3510 | 0 | |||
| 3511 | Programming Mode | |||
| 3513 | 1 | +- | ||
| 3516 | Main Power Mode | <> | 3507 | Transition state (non-operational) |
| 3585 | BIF[3:0]#. The BIF# pin states shall be controlled by the baseboard to allow the baseboard to override the default end point bifurcation for silicon that support bifurcation. Additional combinatorial logic is required and is specific to the card silicon. The combinatorial logic is not covered in this specification. The BIF[3:0]# pins may optionally be hardcoded for baseboards that do not require a dynamic bifurcation override. BIF[2:0]# pins exist on each connector. | <> | 3576 | BIF[2:0]#. The BIF# pin states shall be controlled by the baseboard to allow the baseboard to override the default end point bifurcation for silicon that support bifurcation. Additional combinatorial logic is required and is specific to the card silicon. The combinatorial logic is not covered in this specification. The BIF[2:0]# pins may optionally be hardcoded for baseboards that do not require a dynamic bifurcation override. BIF[2:0]# pins exist on each connector. |
| 3604 | For cases where the baseboard request a link count override (such as requesting a 4-host baseboard requesting 4 x4 operation on a supported card that would otherwise default to a 2 x8 case), the BIF[0:2]# pins shall be asserted as appropriate. Asserting the BIF[0:2]# pins assumes the OCP NIC 3.0 card supports the requested link override. | <> | 3595 | For cases where the baseboard request a link count override (such as requesting a 4-host baseboard requesting 4 x4 operation on a supported card that would otherwise default to a 2 x8 case), the BIF[2:0]# pins shall be asserted as appropriate. Asserting the BIF[2:0]# pins assumes the OCP NIC 3.0 card supports the requested link override. |
| 3605 | Note: For cards that are already powered up, BIF[0:2]# reconfiguration requires a transition back to ID Mode. During this transition, the card power rails are inactive and manageability links may be briefly lost due to the RBT isolation state. | 3596 | Note: For cards that are already powered up, BIF[2:0]# reconfiguration requires a transition back to ID Mode. During this transition, the card power rails are inactive and manageability links may be briefly lost due to the RBT isolation state. | |
| 3606 | The BIF[0:2]# pins must be in their valid states upon the assertion of AUX_PWR_EN. | 3597 | The BIF[2:0]# pins must be in their valid states upon the assertion of AUX_PWR_EN. | |
| 3610 | PERST# shall be deasserted >1 s after NIC_PWR_GOOD assertion as defined in Figure 107. Refer to Section 3.10.1 for timing details. | <> | 3601 | PERST# shall be deasserted >1 s after NIC_PWR_GOOD assertion as defined in Figure 107. Refer to Section 3.11 for timing details. |
| 3786 | There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode (S5), and Main Power Mode (S0). These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 106 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.10.1. | <> | 3777 | There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode (S5), and Main Power Mode (S0). These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 106 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.11. |
| 3841 | Note 1: Only the PRSNTB[0:3]# scan chain signals are valid in ID mode as the OCP NIC 3.0 card power rails have not yet been enabled via the AUX_PWR_EN/MAIN_PWR_EN signals. | <> | 3832 | Note 1: Only the PRSNTB[3:0]# scan chain signals are valid in ID mode as the OCP NIC 3.0 card power rails have not yet been enabled via the AUX_PWR_EN/MAIN_PWR_EN signals. |
| 3849 | The baseboard queries the EEPROM and determines the OCP NIC 3.0 device capabilities. The FRU EEPROM content requirements are defined in Section 4.10.3. Only the card PRSNTB[0:3]# bits are valid on the scan chain in this mode as the OCP NIC 3.0 card power rails have not yet been enabled via the AUX_PWR_EN and MAIN_PWR_EN signals. The WAKE#, TEMP_WARN#, TEMP_CRIT#, Link and Activity bits are invalid and should be masked by the baseboard in ID Mode. | <> | 3840 | The baseboard queries the EEPROM and determines the OCP NIC 3.0 device capabilities. The FRU EEPROM content requirements are defined in Section 4.10.3. Only the card PRSNTB[3:0]# bits are valid on the scan chain in this mode as the OCP NIC 3.0 card power rails have not yet been enabled via the AUX_PWR_EN and MAIN_PWR_EN signals. The WAKE#, TEMP_WARN#, TEMP_CRIT#, Link and Activity bits are invalid and should be masked by the baseboard in ID Mode. |
| 4229 | When the temperature sensor reporting function is implemented, the OCP NIC 3.0 card shall support PLDM for Platform Monitoring and Control (DSP0248 compliant) for temperature reporting. | <> | 4220 | When the temperature sensor reporting function is implemented, the OCP NIC 3.0 card shall support PLDM for Platform Monitoring and Control (DSP0248 compliant) for temperature reporting. Additionally, refer to DSP2054 for the PLDM NIC Modeling scheme. |
| 4234 | Note: Refer to DSP0248 for definitions of the upper warning, upper critical, and upper fatal thresholds. | <> | 4225 | Note: Refer to DSP0248 for definitions of the upper warning, upper critical, and upper fatal thresholds. Additionally, refer to DSP2054 for the PLDM NIC Modeling scheme. |
| 5209 | - Section 3.4.2 – Clarified BIF[0:2]# assertion timing. | <> | 5200 | - Section 3.4.2 – Clarified BIF[2:0]# assertion timing. |
| -+ | 5329 | - General – Fixed Power Sequence Timing Requirements as Heading 2 (was incorrectly changed to Heading 3). Fixed index order for BIF pins as [2:0]. Previous versions of this document had mixed indexes represented as BIF[0:2], and incorrectly as BIF[3:0] in some instances. Fixed index order for PRSNTB pins as [3:0]. | ||
| 5361 | 09/04/2020 | <> | 5353 | 09/15/2020 |