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2 Version 1.00 <> 2 Version 1.0.9
 
    <> 11 1.5        Conventions        15
11 1.5        Background        16   12 1.6        Background        16
12 1.6        Overview        18   13 1.7        Overview        18
13 1.6.1        Mechanical Form Factor Overview        18   14 1.7.1        Mechanical Form Factor Overview        18
14 1.6.2        Electrical Overview        20   15 1.7.2        Electrical Overview        20
15 1.6.2.1        Primary Connector        20   16 1.7.2.1        Primary Connector        20
16 1.6.2.2        Secondary Connector        21   17 1.7.2.2        Secondary Connector        21
17 1.7        Non-NIC Use Cases        21   18 1.8        Non-NIC Use Cases        21
18 2        Mechanical Card Form Factor        22   19 2        Mechanical Card Form Factor        23
19 2.1        Form Factor Options        22   20 2.1        Form Factor Options        23
20 2.1.1        SFF Faceplate Configurations        24   21 2.1.1        SFF Faceplate Configurations        25
21 2.1.2        LFF Faceplate Configurations        28   22 2.1.2        LFF Faceplate Configurations        29
22 2.2        Line Side I/O Implementations        32   23 2.2        Line Side I/O Implementations        33
23 2.3        Top Level Assembly (SFF and LFF)        33   24 2.3        Top Level Assembly (SFF and LFF)        34
24 2.4        Faceplate Subassembly (SFF and LFF)        34   25 2.4        Faceplate Subassembly (SFF and LFF)        35
25 2.4.1        Faceplate Subassembly – Exploded View        34   26 2.4.1        Faceplate Subassembly – Exploded View        35
26 2.4.2        Faceplate Subassembly – Bill of Materials (BOM)        34   27 2.4.2        Faceplate Subassembly – Bill of Materials (BOM)        35
27 2.4.3        SFF Generic I/O Faceplate        37   28 2.4.3        SFF Generic I/O Faceplate        38
28 2.4.4        LFF Generic I/O Faceplate        38   29 2.4.4        LFF Generic I/O Faceplate        39
29 2.4.5        Ejector Lever (SFF)        39   30 2.4.5        Ejector Lever (SFF)        40
30 2.4.6        Ejector Levers (LFF)        40   31 2.4.6        Ejector Levers (LFF)        41
31 2.4.7        Ejector Lock (SFF and LFF)        41   32 2.4.7        Ejector Lock (SFF and LFF)        42
32 2.4.8        Clinch Nut (SFF and LFF)        42   33 2.4.8        Clinch Nut (SFF and LFF)        43
33 2.5        Card Keep Out Zones        43   34 2.5        Card Keep Out Zones        44
34 2.5.1        SFF Keep Out Zones        43   35 2.5.1        SFF Keep Out Zones        44
35 2.5.2        LFF Keep Out Zones        46   36 2.5.2        LFF Keep Out Zones        47
36 2.6        Baseboard Keep Out Zones        49   37 2.6        Baseboard Keep Out Zones        50
37 2.7        Insulation Requirements        50   38 2.7        Insulation Requirements        51
38 2.7.1        SFF Insulator        50   39 2.7.1        SFF Insulator        51
39 2.7.2        LFF Insulator        52   40 2.7.2        LFF Insulator        53
40 2.8        Critical-to-Function (CTF) Dimensions (SFF and LFF)        55   41 2.8        Critical-to-Function (CTF) Dimensions (SFF and LFF)        56
41 2.8.1        CTF Tolerances        55   42 2.8.1        CTF Tolerances        56
42 2.8.2        SFF Pull Tab CTF Dimensions        55   43 2.8.2        SFF Pull Tab CTF Dimensions        56
43 2.8.3        SFF Ejector Latch CTF Dimensions        57   44 2.8.3        SFF Ejector Latch CTF Dimensions        58
44 2.8.4        SFF Internal Lock CTF Dimensions        58   45 2.8.4        SFF Internal Lock CTF Dimensions        59
45 2.8.5        SFF Baseboard CTF Dimensions        59   46 2.8.5        SFF Baseboard CTF Dimensions        60
46 2.8.6        LFF Ejector Latch CTF Dimensions        62   47 2.8.6        LFF Ejector Latch CTF Dimensions        63
47 2.8.7        LFF Baseboard CTF Dimensions        63   48 2.8.7        LFF Baseboard CTF Dimensions        64
48 2.9        Labeling Requirements        66   49 2.9        Labeling Requirements        67
49 2.9.1        General Guidelines for Label Contents        66   50 2.9.1        General Guidelines for Label Contents        67
50 2.9.2        MAC Address Labeling Requirements        67   51 2.9.2        MAC Address Labeling Requirements        68
51 2.9.2.1        MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        68   52 2.9.2.1        MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        69
52 2.9.2.2        MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controllers        68   53 2.9.2.2        MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controllers        69
53 2.9.2.3        MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers        69   54 2.9.2.3        MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers        70
54 2.9.2.4        MAC Address Label Example 4 – Singe Port with Quad Host, Single Managed Controller        69   55 2.9.2.4        MAC Address Label Example 4 – Singe Port with Quad Host, Single Managed Controller        70
55 2.10        Mechanical CAD Package Examples        71   56 2.10        Mechanical CAD Package Examples        72
56 3        Electrical Interface Definition – Card Edge and Baseboard        72   57 3        Electrical Interface Definition – Card Edge and Baseboard        73
57 3.1        Card Edge Gold Finger Requirements        72   58 3.1        Card Edge Gold Finger Requirements        73
58 3.1.1        Gold Finger Mating Sequence        74   59 3.1.1        Gold Finger Mating Sequence        75
59 3.2        Baseboard Connector Requirements        78   60 3.2        Baseboard Connector Requirements        79
60 3.2.1        Right Angle Connector        78   61 3.2.1        Right Angle Connector        79
61 3.2.2        Right Angle Offset        79   62 3.2.2        Right Angle Offset        80
62 3.2.3        Straddle Mount Connector        79   63 3.2.3        Straddle Mount Connector        80
63 3.2.4        Straddle Mount Offset and PCB Thickness Options        81   64 3.2.4        Straddle Mount Offset and PCB Thickness Options        82
64 3.2.5        LFF Connector Locations        82   65 3.2.5        LFF Connector Locations        83
65 3.3        Pin Definition        82   66 3.3        Pin Definition        83
66 3.3.1        Primary Connector        83   67 3.3.1        Primary Connector        84
67 3.3.2        Secondary Connector        85   68 3.3.2        Secondary Connector        86
68 3.4        Signal Descriptions        86   69 3.4        Signal Descriptions        87
69 3.4.1        PCIe Interface Pins        86   70 3.4.1        PCIe Interface Pins        87
70 3.4.2        PCIe Present and Bifurcation Control Pins        92   71 3.4.2        PCIe Present and Bifurcation Control Pins        93
71 3.4.3        SMBus Interface Pins        95   72 3.4.3        SMBus Interface Pins        96
72 3.4.4        NC-SI over RBT Interface Pins        96   73 3.4.4        NC-SI over RBT Interface Pins        97
73 3.4.5        Scan Chain Pins        104   74 3.4.5        Scan Chain Pins        105
74 3.4.6        Power Supply Pins        111   75 3.4.6        Power Supply Pins        113
75 3.4.7        USB 2.0 (A68/A69) – Primary Connector Only        117   76 3.4.7        USB 2.0 (A68/A69) – Primary Connector Only        119
76 3.4.8        UART (A68/A69) – Secondary Connector Only        119   77 3.4.8        UART (A68/A69) – Secondary Connector Only        121
77 3.4.9        RFU[1:4] Pins        121   78 3.4.9        RFU[1:4] Pins        123
78 3.5        PCIe Bifurcation Mechanism        122   79 3.5        PCIe Bifurcation Mechanism        124
79 3.5.1        PCIe OCP NIC 3.0 Card to Baseboard Bifurcation Configuration (PRSNTA#, PRSNTB[3:0]#)        122   80 3.5.1        PCIe OCP NIC 3.0 Card to Baseboard Bifurcation Configuration (PRSNTA#, PRSNTB[3:0]#)        124
80 3.5.2        PCIe Baseboard to OCP NIC 3.0 Card Bifurcation Configuration (BIF[2:0]#)        122   81 3.5.2        PCIe Baseboard to OCP NIC 3.0 Card Bifurcation Configuration (BIF[2:0]#)        124
81 3.5.3        PCIe Bifurcation Decoder        123   82 3.5.3        PCIe Bifurcation Decoder        125
82 3.5.4        Bifurcation Detection Flow        125   83 3.5.4        Bifurcation Detection Flow        127
83 3.5.5        PCIe Bifurcation Examples        126   84 3.5.5        PCIe Bifurcation Examples        128
84 3.5.5.1        Single Host (1 x16) Baseboard with a 1 x16 OCP NIC 3.0 Card (Single Controller)        126   85 3.5.5.1        Single Host (1 x16) Baseboard with a 1 x16 OCP NIC 3.0 Card (Single Controller)        128
85 3.5.5.2        Single Host (2 x8) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controllers)        127   86 3.5.5.2        Single Host (2 x8) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controllers)        129
86 3.5.5.3        Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Single Controller)        128   87 3.5.5.3        Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Single Controller)        130
87 3.5.5.4        Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Quad Controllers)        129   88 3.5.5.4        Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Quad Controllers)        131
88 3.5.5.5        Single Host (1 x16, no Bifurcation) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controller)        130   89 3.5.5.5        Single Host (1 x16, no Bifurcation) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controller)        132
89 3.6        PCIe REFCLK and PERST# Mapping        131   90 3.6        PCIe REFCLK and PERST# Mapping        133
90 3.6.1        SFF PCIe REFCLK and PERST# Mapping        132   91 3.6.1        SFF PCIe REFCLK and PERST# Mapping        134
91 3.6.2        LFF PCIe REFCLK and PERST# Mapping        135   92 3.6.2        LFF PCIe REFCLK and PERST# Mapping        137
92 3.6.3        REFCLK and PERST# Mapping Expansion        137   93 3.6.3        REFCLK and PERST# Mapping Expansion        139
93 3.7        Port Numbering and LED Implementations        138   94 3.7        Port Numbering and LED Implementations        140
94 3.7.1        OCP NIC 3.0 Port Naming and Port Numbering        138   95 3.7.1        OCP NIC 3.0 Port Naming and Port Numbering        140
95 3.7.2        OCP NIC 3.0 Card LED Configuration        138   96 3.7.2        OCP NIC 3.0 Card LED Configuration        140
96 3.7.3        OCP NIC 3.0 Card LED Ordering        140   97 3.7.3        OCP NIC 3.0 Card LED Ordering        142
97 3.7.4        Baseboard LEDs Configuration over the Scan Chain        141   98 3.7.4        Baseboard LEDs Configuration over the Scan Chain        143
98 3.8        Power State Machine        143   99 3.8        Power State Machine        145
99 3.8.1        NIC Power Off        144   100 3.8.1        NIC Power Off        146
100 3.8.2        ID Mode        144   101 3.8.2        ID Mode        146
101 3.8.3        Aux Power Mode (S5)        144   102 3.8.3        Aux Power Mode (S5)        146
102 3.8.4        Main Power Mode (S0)        145   103 3.8.4        Main Power Mode (S0)        147
103 3.8.5        Programming Mode        145   104 3.8.5        Programming Mode        147
104 3.9        Power Supply Rail Requirements and Slot Power Envelopes        146   105 3.9        Power Supply Rail Requirements and Slot Power Envelopes        148
105 3.10        Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails        147   106 3.10        Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails        149
106 3.11        Power Sequence Timing Requirements        148   107 3.10.1        Power Sequence Timing Requirements        150
107 3.12        Digital I/O Specifications        152   108 3.11        Digital I/O Specifications        154
108 4        Management and Pre-OS Requirements        153   109 4        Management and Pre-OS Requirements        155
109 4.1        Sideband Management Interface and Transport        153   110 4.1        Sideband Management Interface and Transport        155
110 4.2        NC-SI Traffic        154   111 4.2        NC-SI Traffic        156
111 4.3        Management Controller (MC) MAC Address Provisioning        154   112 4.3        Management Controller (MC) MAC Address Provisioning        156
112 4.4        ASIC Die Temperature Reporting        156   113 4.4        ASIC Die Temperature Reporting        158
113 4.5        Power Consumption Reporting        158   114 4.5        Power Consumption Reporting        161
114 4.6        Pluggable Transceiver Module Status and Temperature Reporting        159   115 4.6        Pluggable Transceiver Module Status and Temperature Reporting        161
115 4.7        Management and Pre-OS Firmware Inventory and Update        159   116 4.7        Management and Pre-OS Firmware Inventory and Update        162
116 4.7.1        Secure Firmware        160   117 4.7.1        Secure Firmware        162
117 4.7.2        Firmware Inventory        160   118 4.7.2        Firmware Inventory        163
118 4.7.3        Firmware Inventory and Update in Multi-Host Environments        160   119 4.7.3        Firmware Inventory and Update in Multi-Host Environments        163
119 4.8        NC-SI Package Addressing and Hardware Arbitration Requirements        161   120 4.8        NC-SI Package Addressing and Hardware Arbitration Requirements        164
120 4.8.1        NC-SI over RBT Package Addressing        161   121 4.8.1        NC-SI over RBT Package Addressing        164
121 4.8.2        Arbitration Ring Connections        161   122 4.8.2        Arbitration Ring Connections        164
122 4.9        SMBus 2.0 Addressing Requirements        161   123 4.9        SMBus 2.0 Addressing Requirements        164
123 4.9.1        SMBus Address Map        162   124 4.9.1        SMBus Address Map        165
124 4.10        FRU EEPROM        162   125 4.10        FRU EEPROM        165
125 4.10.1        FRU EEPROM Addressing and Size        162   126 4.10.1        FRU EEPROM Addressing and Size        165
126 4.10.2        FRU EEPROM Write Protection        164   127 4.10.2        FRU EEPROM Write Protection        167
127 4.10.3        FRU EEPROM Content Requirements        164   128 4.10.3        FRU EEPROM Content Requirements        167
128 4.10.4        FRU Template        170   129 4.10.4        FRU Template        174
129 5        Routing Guidelines and Signal Integrity Considerations        171   130 5        Routing Guidelines and Signal Integrity Considerations        174
130 5.1        NC-SI over RBT        171   131 5.1        NC-SI over RBT        174
131 5.1.1        SFF Baseboard Requirements        172   132 5.1.1        SFF Baseboard Requirements        176
132 5.1.2        LFF Baseboard Requirements        173   133 5.1.2        LFF Baseboard Requirements        176
133 5.1.3        SFF OCP NIC 3.0 Card Requirements        173   134 5.1.3        SFF OCP NIC 3.0 Card Requirements        177
134 5.1.4        LFF OCP NIC 3.0 Card Requirements        174   135 5.1.4        LFF OCP NIC 3.0 Card Requirements        178
135 5.2        SMBus 2.0        174   136 5.2        SMBus 2.0        178
136 5.3        PCIe        175   137 5.3        PCIe        179
137 5.3.1        Channel Requirements        175   138 5.3.1        Channel Requirements        179
138 5.3.1.1        REFCLK requirements        175   139 5.3.1.1        REFCLK requirements        179
139 5.3.1.2        Add-in Card Electrical Budgets        175   140 5.3.1.2        Add-in Card Electrical Budgets        179
140 5.3.1.3        Baseboard Channel Budget        175   141 5.3.1.3        Baseboard Channel Budget        180
141 5.3.1.4        SFF-TA-1002 Connector Channel Budget        175   142 5.3.1.4        SFF-TA-1002 Connector Channel Budget        180
142 5.3.1.5        Differential Impedance (Informative)        175   143 5.3.1.5        Differential Impedance (Informative)        180
143 5.3.2        Test Fixtures        176   144 5.3.2        Test Fixtures        180
144 5.3.2.1        Compliance Load Board (CLB)        176   145 5.3.2.1        Compliance Load Board (CLB)        180
145 5.3.2.2        Compliance Baseboard (CBB)        177   146 5.3.2.2        Compliance Baseboard (CBB)        182
146 5.3.3        Test Methodology        177   147 5.3.3        Test Methodology        182
147 5.3.3.1        Test Setup        177   148 5.3.3.1        Test Setup        182
148 6        Thermal and Environmental        178   149 6        Thermal and Environmental        184
149 6.1        Airflow Direction        178   150 6.1        Airflow Direction        184
150 6.1.1        Hot Aisle Cooling        178   151 6.1.1        Hot Aisle Cooling        184
151 6.1.2        Cold Aisle Cooling        179   152 6.1.2        Cold Aisle Cooling        185
152 6.2        Thermal Design Guidelines        180   153 6.2        Thermal Design Guidelines        186
153 6.2.1        SFF Card ASIC Cooling – Hot Aisle        180   154 6.2.1        SFF Card ASIC Cooling – Hot Aisle        186
154 6.2.2        LFF Card ASIC Cooling – Hot Aisle        184   155 6.2.2        LFF Card ASIC Cooling – Hot Aisle        190
155 6.2.3        SFF Card ASIC Cooling – Cold Aisle        186   156 6.2.3        SFF Card ASIC Cooling – Cold Aisle        192
156 6.2.4        LFF Card ASIC Cooling – Cold Aisle        189   157 6.2.4        LFF Card ASIC Cooling – Cold Aisle        195
157 6.3        Thermal Simulation (CFD) Modeling        191   158 6.3        Thermal Simulation (CFD) Modeling        197
158 6.4        Thermal Test Fixture        191   159 6.4        Thermal Test Fixture        197
159 6.4.1        Test Fixture for SFF Card        192   160 6.4.1        Test Fixture for SFF Card        198
160 6.4.2        Test Fixture for LFF Card        194   161 6.4.2        Test Fixture for LFF Card        200
161 6.4.3        Test Fixture Airflow Direction        196   162 6.4.3        Test Fixture Airflow Direction        202
162 6.4.4        Thermal Test Fixture Candlestick Sensors        196   163 6.4.4        Thermal Test Fixture Candlestick Sensors        202
163 6.5        Card Sensor Requirements        198   164 6.5        Card Sensor Requirements        204
164 6.6        Card Cooling Tiers        198   165 6.6        Card Cooling Tiers        204
165 6.7        Non-Operational Shock & Vibration Testing        200   166 6.7        Non-Operational Shock & Vibration Testing        206
166 6.7.1        Shock & Vibe Test Fixture        200   167 6.7.1        Shock & Vibe Test Fixture        206
167 6.7.2        Test Procedure        201   168 6.7.2        Test Procedure        207
168 6.8        Dye and Pull Test Method        203   169 6.8        Dye and Pull Test Method        209
169 6.9        Gold Finger Plating Requirements        205   170 6.9        Gold Finger Plating Requirements        211
170 6.9.1        Host Side Gold Finger Plating Requirements        205   171 6.9.1        Host Side Gold Finger Plating Requirements        211
171 6.9.2        Line Side Gold Finger Durability Requirements        205   172 6.9.2        Line Side Gold Finger Durability Requirements        211
172 7        Regulatory        206   173 7        Regulatory        212
173 7.1        Required Compliance        206   174 7.1        Required Compliance        212
174 7.1.1        Required Environmental Compliance        206   175 7.1.1        Required Environmental Compliance        212
175 7.1.2        Required EMC Compliance        206   176 7.1.2        Required EMC Compliance        212
176 7.1.3        Required Product Safety Compliance        207   177 7.1.3        Required Product Safety Compliance        213
177 7.1.4        Required Immunity (ESD) Compliance        207   178 7.1.4        Required Immunity (ESD) Compliance        213
178 7.2        Recommended Compliance        208   179 7.2        Recommended Compliance        214
179 7.2.1        Recommended Environmental Compliance        208   180 7.2.1        Recommended Environmental Compliance        214
180 7.2.2        Recommended EMC Compliance        208   181 7.2.2        Recommended EMC Compliance        214
181 8        Revision History        209   182 8        Revision History        215
182 8.1        Document Revision History        209   183 8.1        Document Revision History        215
183 8.2        FRU Content Revision History        215   184 8.2        FRU Content Revision History        222
 
188 Figure 4: Primary Connector (4C+) and Secondary Connector (4C) (LFF) OCP NIC 3.0 Cards        22 <> 189 Figure 4: Primary Connector (4C+) and Secondary Connector (4C) (LFF) OCP NIC 3.0 Cards        23
189 Figure 5: Primary Connector (4C+) Only (LFF) OCP NIC 3.0 Cards        23   190 Figure 5: Primary Connector (4C+) Only (LFF) OCP NIC 3.0 Cards        24
190 Figure 6: Primary Connector (4C+) with 4C and 2C (SFF) OCP NIC 3.0 Cards        23   191 Figure 6: Primary Connector (4C+) with 4C and 2C (SFF) OCP NIC 3.0 Cards        24
191 Figure 7: SFF NIC Configuration Views        25   192 Figure 7: SFF NIC Configuration Views        26
192 Figure 8: SFF NIC Line Side 3D Views        26   193 Figure 8: SFF NIC Line Side 3D Views        27
193 Figure 9: SFF NIC Chassis Mounted 3D Views        27   194 Figure 9: SFF NIC Chassis Mounted 3D Views        28
194 Figure 10: LFF NIC Configuration Views        29   195 Figure 10: LFF NIC Configuration Views        30
195 Figure 11: LFF NIC Line Side 3D Views        30   196 Figure 11: LFF NIC Line Side 3D Views        31
196 Figure 12: LFF NIC Chassis Mounted 3D Views        31   197 Figure 12: LFF NIC Chassis Mounted 3D Views        32
197 Figure 13: PBA Exploded Views (SFF and LFF)        33   198 Figure 13: PBA Exploded Views (SFF and LFF)        34
198 Figure 14: Faceplate Assembly Exploded Views (SFF and LFF)        34   199 Figure 14: Faceplate Assembly Exploded Views (SFF and LFF)        35
199 Figure 15: SFF Generic I/O Faceplate with Pulltab Version (2D View)        37   200 Figure 15: SFF Generic I/O Faceplate with Pulltab Version (2D View)        38
200 Figure 16: SFF Generic I/O Faceplate – Ejector Version (2D View)        37   201 Figure 16: SFF Generic I/O Faceplate – Ejector Version (2D View)        38
201 Figure 17: SFF Generic I/O Faceplate – Internal Lock Version (2D View)        38   202 Figure 17: SFF Generic I/O Faceplate – Internal Lock Version (2D View)        39
202 Figure 18: LFF Generic I/O Faceplate – Ejector Version (2D View)        38   203 Figure 18: LFF Generic I/O Faceplate – Ejector Version (2D View)        39
203 Figure 19: SFF I/O Faceplate – Ejector Lever (2D View)        39   204 Figure 19: SFF I/O Faceplate – Ejector Lever (2D View)        40
204 Figure 20: LFF I/O Faceplate – Ejector Lever (2D View)        40   205 Figure 20: LFF I/O Faceplate – Ejector Lever (2D View)        41
205 Figure 21: Ejector Lock        41   206 Figure 21: Ejector Lock        42
206 Figure 22: Clinch Nut Option A        42   207 Figure 22: Clinch Nut Option A        43
207 Figure 23: Clinch Nut Option B        42   208 Figure 23: Clinch Nut Option B        43
208 Figure 24: SFF Keep Out Zone – Top View        43   209 Figure 24: SFF Keep Out Zone – Top View        44
209 Figure 25: SFF Keep Out Zone – Top View – Detail A        44   210 Figure 25: SFF Keep Out Zone – Top View – Detail A        45
210 Figure 26: SFF Keep Out Zone – Bottom View        44   211 Figure 26: SFF Keep Out Zone – Bottom View        45
211 Figure 27: SFF Keep Out Zone – Side View        45   212 Figure 27: SFF Keep Out Zone – Side View        46
212 Figure 28: SFF Keep Out Zone – Side View – Detail D        45   213 Figure 28: SFF Keep Out Zone – Side View – Detail D        46
213 Figure 29: LFF Keep Out Zone – Top View        46   214 Figure 29: LFF Keep Out Zone – Top View        47
214 Figure 30: LFF Keep Out Zone – Top View – Detail A        47   215 Figure 30: LFF Keep Out Zone – Top View – Detail A        48
215 Figure 31: LFF Keep Out Zone – Bottom View        48   216 Figure 31: LFF Keep Out Zone – Bottom View        49
216 Figure 32: LFF Keep Out Zone – Side View        48   217 Figure 32: LFF Keep Out Zone – Side View        49
217 Figure 33: LFF Keep Out Zone – Side View – Detail D        49   218 Figure 33: LFF Keep Out Zone – Side View – Detail D        50
218 Figure 34: SFF Bottom Side Insulator (3D View)        50   219 Figure 34: SFF Bottom Side Insulator (3D View)        51
219 Figure 35: SFF Bottom Side Insulator (Top and Side View)        51   220 Figure 35: SFF Bottom Side Insulator (Top and Side View)        52
220 Figure 36: SFF Bottom Side Insulator (alternate) (Top and Side View)        52   221 Figure 36: SFF Bottom Side Insulator (alternate) (Top and Side View)        53
221 Figure 37: LFF Bottom Side Insulator (3D View)        52   222 Figure 37: LFF Bottom Side Insulator (3D View)        53
222 Figure 38: LFF Bottom Side Insulator (Top and Side View)        53   223 Figure 38: LFF Bottom Side Insulator (Top and Side View)        54
223 Figure 39: LFF Bottom Side Insulator (alternate) (Top and Side View)        54   224 Figure 39: LFF Bottom Side Insulator (alternate) (Top and Side View)        55
224 Figure 40: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View)        55   225 Figure 40: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View)        56
225 Figure 41: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View)        56   226 Figure 41: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View)        57
226 Figure 42: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View)        56   227 Figure 42: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View)        57
227 Figure 43: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View)        57   228 Figure 43: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View)        58
228 Figure 44: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)        57   229 Figure 44: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)        58
229 Figure 45: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)        58   230 Figure 45: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)        59
230 Figure 46: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View)        58   231 Figure 46: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View)        59
231 Figure 47: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Front View)        59   232 Figure 47: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Front View)        60
232 Figure 48: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Side View)        59   233 Figure 48: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Side View)        60
233 Figure 49: SFF Baseboard Chassis CTF Dimensions (Rear View)        59   234 Figure 49: SFF Baseboard Chassis CTF Dimensions (Rear View)        60
234 Figure 50: SFF Baseboard Chassis to Card Thumb Screw CTF Dimensions (Side View)        60   235 Figure 50: SFF Baseboard Chassis to Card Thumb Screw CTF Dimensions (Side View)        61
235 Figure 51: SFF Baseboard Chassis to Ejector lever Card CTF Dimensions (Side View)        60   236 Figure 51: SFF Baseboard Chassis to Ejector lever Card CTF Dimensions (Side View)        61
236 Figure 52: SFF Baseboard Chassis CTF Dimensions (Rear Rail Guide View)        60   237 Figure 52: SFF Baseboard Chassis CTF Dimensions (Rear Rail Guide View)        61
237 Figure 53: SFF Baseboard Chassis CTF Dimensions (Rail Guide Detail) – Detail C        61   238 Figure 53: SFF Baseboard Chassis CTF Dimensions (Rail Guide Detail) – Detail C        62
238 Figure 54: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View)        62   239 Figure 54: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View)        63
239 Figure 55: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)        62   240 Figure 55: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View)        63
240 Figure 56: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)        63   241 Figure 56: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View)        64
241 Figure 57: LFF Baseboard Chassis CTF Dimensions (Rear View)        63   242 Figure 57: LFF Baseboard Chassis CTF Dimensions (Rear View)        64
242 Figure 58: LFF Baseboard Chassis CTF Dimensions (Side View)        64   243 Figure 58: LFF Baseboard Chassis CTF Dimensions (Side View)        65
243 Figure 59: LFF Baseboard Chassis CTF Dimensions (Rail Guide View)        64   244 Figure 59: LFF Baseboard Chassis CTF Dimensions (Rail Guide View)        65
244 Figure 60: LFF Baseboard Chassis CTF Dimensions (Rail Guide – Detail C)        64   245 Figure 60: LFF Baseboard Chassis CTF Dimensions (Rail Guide – Detail C)        65
245 Figure 61: SFF Label Area Example        66   246 Figure 61: SFF Label Area Example        67
246 Figure 62: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        68   247 Figure 62: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        69
247 Figure 63: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller        69   248 Figure 63: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller        70
248 Figure 64: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers        69   249 Figure 64: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers        70
249 Figure 65: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller        70   250 Figure 65: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller        71
250 Figure 66: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller        70   251 Figure 66: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller        71
251 Figure 67: SFF Primary Connector Gold Finger Dimensions – x16 – Top Side (“B” Pins)        72   252 Figure 67: SFF Primary Connector Gold Finger Dimensions – x16 – Top Side (“B” Pins)        73
252 Figure 68: SFF Primary Connector Card Profile Dimensions        73   253 Figure 68: SFF Primary Connector Card Profile Dimensions        74
253 Figure 69: SFF Primary Conector Gold Finger - Detail D        73   254 Figure 69: SFF Primary Conector Gold Finger - Detail D        74
254 Figure 70: LFF Gold Finger Dimensions – x32 – Top Side (“B” Pins)        74   255 Figure 70: LFF Gold Finger Dimensions – x32 – Top Side (“B” Pins)        75
255 Figure 71: LFF Gold Finger Dimensions – x32 – Bottom Side (“A” Pins)        74   256 Figure 71: LFF Gold Finger Dimensions – x32 – Bottom Side (“A” Pins)        75
256 Figure 72: 168-pin Base Board Primary Connector – Right Angle        78   257 Figure 72: 168-pin Base Board Primary Connector – Right Angle        79
257 Figure 73: 140-pin Base Board Secondary Connector – Right Angle        79   258 Figure 73: 140-pin Base Board Secondary Connector – Right Angle        80
258 Figure 74: OCP NIC 3.0 Card and Host Offset for Right Angle Connectors        79   259 Figure 74: OCP NIC 3.0 Card and Host Offset for Right Angle Connectors        80
259 Figure 75: 168-pin Base Board Primary Connector – Straddle Mount        80   260 Figure 75: 168-pin Base Board Primary Connector – Straddle Mount        81
260 Figure 76: 140-pin Base Board Secondary Connector – Straddle Mount        80   261 Figure 76: 140-pin Base Board Secondary Connector – Straddle Mount        81
261 Figure 77: OCP NIC 3.0 Card and Baseboard PCB Thickness Options for Straddle Mount Connectors        81   262 Figure 77: OCP NIC 3.0 Card and Baseboard PCB Thickness Options for Straddle Mount Connectors        82
262 Figure 78: 0 mm Offset (Coplanar) for 0.062” Thick Baseboards        81   263 Figure 78: 0 mm Offset (Coplanar) for 0.062” Thick Baseboards        82
263 Figure 79: 0.3 mm Offset for 0.076” Thick Baseboards        82   264 Figure 79: 0.3 mm Offset for 0.076” Thick Baseboards        83
264 Figure 80: Primary and Secondary Connector Locations for LFF Support with Right Angle Connectors        82   265 Figure 80: Primary and Secondary Connector Locations for LFF Support with Right Angle Connectors        83
265 Figure 81: Primary and Secondary Connector Locations for LFF Support with Straddle Mount Connectors        82   266 Figure 81: Primary and Secondary Connector Locations for LFF Support with Straddle Mount Connectors        83
266 Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[0:2]#)        94   267 Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[0:2]#)        95
267 Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[0:2]#)        94   268 Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[0:2]#)        95
268 Figure 84: Example SMBus Connections        96   269 Figure 84: Example SMBus Connections        97
269 Figure 85: NC-SI over RBT Connection Example – Single Primary Connector        102   270 Figure 85: NC-SI over RBT Connection Example – Single Primary Connector        103
270 Figure 86: NC-SI over RBT Connection Example – Dual Primary Connectors        103   271 Figure 86: NC-SI over RBT Connection Example – Dual Primary Connectors        104
271 Figure 87: Example Scan Chain Timing Diagram        106   272 Figure 87: Scan Chain Timing Diagram Example 1        107
      273 Figure 88: Scan Chain Timing Diagram Example 2        107
272 Figure 88: Scan Chain Connection Example        111   274 Figure 88: Scan Chain Connection Example        113
273 Figure 89: Example Power Supply Topology        116   275 Figure 89: Example Power Supply Topology        118
274 Figure 90: USB 2.0 Connection Example – Basic Connectivity        118   276 Figure 90: USB 2.0 Connection Example – Basic Connectivity        120
275 Figure 91: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity        118   277 Figure 91: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity        120
276 Figure 92: UART Connection Example        120   278 Figure 92: UART Connection Example        122
277 Figure 93: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller)        126   279 Figure 93: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller)        128
278 Figure 94: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)        127   280 Figure 94: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)        129
279 Figure 95: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller)        128   281 Figure 95: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller)        130
280 Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers)        129   282 Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers)        131
281 Figure 97: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)        130   283 Figure 97: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)        132
282 Figure 98: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links        132   284 Figure 98: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links        134
283 Figure 99: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links        133   285 Figure 99: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links        135
284 Figure 100: SFF PCIe REFCLK Mapping – Quad Host – 4 Links        134   286 Figure 100: SFF PCIe REFCLK Mapping – Quad Host – 4 Links        136
285 Figure 101: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links        135   287 Figure 101: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links        137
286 Figure 102: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links        136   288 Figure 102: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links        138
287 Figure 103: LFF PCIe REFCLK Mapping – Quad Host – 4 Links        137   289 Figure 103: LFF PCIe REFCLK Mapping – Quad Host – 4 Links        139
288 Figure 104: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement        141   290 Figure 104: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement        143
289 Figure 105: Baseboard Power States        143   291 Figure 105: Baseboard Power States        145
290 Figure 106: Power-Up Sequencing – Normal Operation        148   292 Figure 106: Power-Up Sequencing – Normal Operation        150
291 Figure 107: Power-Down Sequencing – Normal Operation        149   293 Figure 107: Power-Down Sequencing – Normal Operation        151
292 Figure 108: Programming Mode Sequencing        150   294 Figure 108: Programming Mode Sequencing        152
293 Figure 109: FRU EEPROM Writes with Double Byte Addressing        163   295 Figure 109: FRU EEPROM Writes with Double Byte Addressing        166
294 Figure 110: FRU EEPROM Reads with Double Byte Addressing        163   296 Figure 110: FRU EEPROM Reads with Double Byte Addressing        166
295 Figure 111: FRU Update Flow        164   297 Figure 111: FRU Update Flow        167
296 Figure 112: NC-SI over RBT Timing Budget Topology        172   298 Figure 112: NC-SI over RBT Timing Budget Topology        175
297 Figure 113: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer        174   299 Figure 113: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer        178
298 Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer        174   300 Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer        178
299 Figure 115: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF        176   301 Figure 115: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF        180
300 Figure 116: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF        177   302 Figure 116: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF        182
301 Figure 117: Airflow Direction for Hot Aisle Cooling (SFF and LFF)        178   303 Figure 117: Airflow Direction for Hot Aisle Cooling (SFF and LFF)        184
302 Figure 118: Airflow Direction for Cold Aisle Cooling (SFF and LFF)        179   304 Figure 118: Airflow Direction for Cold Aisle Cooling (SFF and LFF)        185
303 Figure 119: ASIC Supportable Power for Hot Aisle Cooling – SFF        180   305 Figure 119: ASIC Supportable Power for Hot Aisle Cooling – SFF        186
304 Figure 120: OCP NIC 3.0 SFF Reference Design and CFD Geometry        181   306 Figure 120: OCP NIC 3.0 SFF Reference Design and CFD Geometry        187
305 Figure 121: Server System Airflow Capability – SFF Card Hot Aisle Cooling        182   307 Figure 121: Server System Airflow Capability – SFF Card Hot Aisle Cooling        188
306 Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode        183   308 Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode        189
307 Figure 123: ASIC Supportable Power for Hot Aisle Cooling – LFF Card        184   309 Figure 123: ASIC Supportable Power for Hot Aisle Cooling – LFF Card        190
308 Figure 124: OCP NIC 3.0 LFF Reference Design and CFD Geometry        184   310 Figure 124: OCP NIC 3.0 LFF Reference Design and CFD Geometry        190
309 Figure 125: Server System Airflow Capability – LFF Card Hot Aisle Cooling        186   311 Figure 125: Server System Airflow Capability – LFF Card Hot Aisle Cooling        192
310 Figure 126: ASIC Supportable Power for Cold Aisle Cooling – SFF Card        187   312 Figure 126: ASIC Supportable Power for Cold Aisle Cooling – SFF Card        193
311 Figure 127: Server System Airflow Capability – SFF Cold Aisle Cooling        188   313 Figure 127: Server System Airflow Capability – SFF Cold Aisle Cooling        194
312 Figure 128: ASIC Supportable Power Comparison – SFF Card        188   314 Figure 128: ASIC Supportable Power Comparison – SFF Card        194
313 Figure 129: ASIC Supportable Power for Cold Aisle Cooling – LFF Card        189   315 Figure 129: ASIC Supportable Power for Cold Aisle Cooling – LFF Card        195
314 Figure 130: Server System Airflow Capability – LFF Cold Aisle Cooling        190   316 Figure 130: Server System Airflow Capability – LFF Cold Aisle Cooling        196
315 Figure 131: ASIC Supportable Power Comparison – LFF Card        190   317 Figure 131: ASIC Supportable Power Comparison – LFF Card        196
316 Figure 132: SFF Thermal Test Fixture Preliminary Design        192   318 Figure 132: SFF Thermal Test Fixture Preliminary Design        198
317 Figure 133: SFF Thermal Test Fixture Preliminary Design – Cover Removed        193   319 Figure 133: SFF Thermal Test Fixture Preliminary Design – Cover Removed        199
318 Figure 134: SFF Card Thermal Test Fixture PCB        193   320 Figure 134: SFF Card Thermal Test Fixture PCB        199
319 Figure 135: LFF Card Thermal Test Fixture Design        194   321 Figure 135: LFF Card Thermal Test Fixture Design        200
320 Figure 136: LFF Card Thermal Test Fixture Design – Cover Removed        194   322 Figure 136: LFF Card Thermal Test Fixture Design – Cover Removed        200
321 Figure 137: LFF Card Thermal Test Fixture PCB        195   323 Figure 137: LFF Card Thermal Test Fixture PCB        201
322 Figure 138: Thermal Test Fixture Airflow Direction        196   324 Figure 138: Thermal Test Fixture Airflow Direction        202
323 Figure 139: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow        197   325 Figure 139: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow        203
324 Figure 140: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow        197   326 Figure 140: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow        203
325 Figure 141: Graphical View of Card Cooling Tiers        199   327 Figure 141: Graphical View of Card Cooling Tiers        205
326 Figure 142: Typical Operating Range for Hot Aisle Configurations        199   328 Figure 142: Typical Operating Range for Hot Aisle Configurations        205
327 Figure 143: Typical Operating Range for Cold Aisle Configurations        200   329 Figure 143: Typical Operating Range for Cold Aisle Configurations        206
328 Figure 144: SFF Shock and Vibe Fixture        201   330 Figure 144: SFF Shock and Vibe Fixture        207
329 Figure 145: LFF Shock and Vibe Fixture        201   331 Figure 145: LFF Shock and Vibe Fixture        207
330 Figure 146: Dye and Pull Type Locations        204   332 Figure 146: Dye and Pull Type Locations        210
331 Figure 147: Dye Coverage Percentage        204   333 Figure 147: Dye Coverage Percentage        210
 
333 Table 1: Acknowledgements – By Company        11 <> 335 Table 1: Acknowledgements – Current Contributors – By Company        11
334 Table 2: Acronyms        14   336 Table 3: Acronyms        14
335 Table 3: OCP 3.0 Form Factor Dimensions        19   337 Table 4: OCP 3.0 Form Factor Dimensions        19
336 Table 4: Baseboard to OCP NIC Form Factor Compatibility Chart        19   338 Table 5: Baseboard to OCP NIC Form Factor Compatibility Chart        19
337 Table 5: Example Non-NIC Use Cases        21   339 Table 6: Example Non-NIC Use Cases        21
338 Table 6: OCP NIC 3.0 Card Definitions        24   340 Table 7: OCP NIC 3.0 Card Definitions        25
339 Table 7: OCP NIC 3.0 Line Side I/O Implementations        32   341 Table 8: OCP NIC 3.0 Line Side I/O Implementations        33
340 Table 8: Line Side I/O Cross Reference to Industry Standards        32   342 Table 9: Line Side I/O Cross Reference to Industry Standards        33
341 Table 9: Bill of Materials for the SFF and LFF Faceplate Assemblies        35   343 Table 10: Bill of Materials for the SFF and LFF Faceplate Assemblies        36
342 Table 10: CTF Default Tolerances (SFF and LFF OCP NIC 3.0)        55   344 Table 11: CTF Default Tolerances (SFF and LFF OCP NIC 3.0)        56
343 Table 11: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        68   345 Table 12: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller        69
344 Table 12: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller        68   346 Table 13: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller        69
345 Table 13: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controller        69   347 Table 14: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controller        70
346 Table 14: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller        70   348 Table 15: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller        71
347 Table 15: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller        70   349 Table 16: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller        71
348 Table 16: NIC Implementation Examples and 3D CAD        71   350 Table 17: NIC Implementation Examples and 3D CAD        72
349 Table 17: Contact Mating Positions for the Primary Connector        74   351 Table 18: Contact Mating Positions for the Primary Connector        75
350 Table 18: Contact Mating Positions for the Secondary Connector        76   352 Table 19: Contact Mating Positions for the Secondary Connector        77
351 Table 19: Right Angle Connector Options        78   353 Table 20: Right Angle Connector Options        79
352 Table 20: Straddle Mount Connector Options        79   354 Table 21: Straddle Mount Connector Options        80
353 Table 21: Primary Connector Pin Definition (x16) (4C+)        83   355 Table 22: Primary Connector Pin Definition (x16) (4C+)        84
354 Table 22: Secondary Connector Pin Definition (x16) (4C)        85   356 Table 23: Secondary Connector Pin Definition (x16) (4C)        86
355 Table 23: Pin Descriptions – PCIe        86   357 Table 24: Pin Descriptions – PCIe        87
356 Table 24: Pin Descriptions – PCIe Present and Bifurcation Control Pins        92   358 Table 25: Pin Descriptions – PCIe Present and Bifurcation Control Pins        93
357 Table 25: Pin Descriptions – SMBus        95   359 Table 26: Pin Descriptions – SMBus        96
358 Table 26: Pin Descriptions – NC-SI over RBT        96   360 Table 27: Pin Descriptions – NC-SI over RBT        97
359 Table 27: Pin Descriptions – Scan Chain        104   361 Table 28: Pin Descriptions – Scan Chain        105
360 Table 28: Scan Chain Timing Requirements – Baseboard Side        106   362 Table 29: Scan Chain Timing Requirements – Baseboard Side        107
361 Table 29: Scan Chain Timing Requirements – OCP NIC 3.0 Card Side        106   363 Table 30: Scan Chain Timing Requirements – OCP NIC 3.0 Card Side        107
362 Table 30: Pin Descriptions – Scan Chain DATA_OUT Bit Definition        106   364 Table 31: Pin Descriptions – Scan Chain DATA_OUT Bit Definition        108
363 Table 31: Pin Descriptions – Scan Chain DATA_IN Bit Definition        107   365 Table 32: Pin Descriptions – Scan Chain DATA_IN Bit Definition        108
364 Table 32: Pin Descriptions – Power        112   366 Table 33: Pin Descriptions – Power        114
365 Table 33: Pin Descriptions – USB 2.0 – Primary Connector only        117   367 Table 34: Pin Descriptions – USB 2.0 – Primary Connector only        119
366 Table 34: Pin Descriptions – UART – Secondary Connector Only        119   368 Table 35: Pin Descriptions – UART – Secondary Connector Only        121
367 Table 35: Pin Descriptions – RFU[1:4]        121   369 Table 36: Pin Descriptions – RFU[1:4]        123
368 Table 36: PCIe Bifurcation Decoder for x32, x16, x8, x4, x2 and x1 Card Widths        124   370 Table 37: PCIe Bifurcation Decoder for x32, x16, x8, x4, x2 and x1 Card Widths        126
369 Table 37: PCIe REFCLK and PERST Associations        131   371 Table 38: PCIe REFCLK and PERST Associations        133
370 Table 38: SFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links        131   372 Table 39: SFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links        133
371 Table 39: LFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2, 4 and 8 Links        131   373 Table 40: LFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2, 4 and 8 Links        133
372 Table 40: OCP NIC 3.0 Card LED Configuration with Two Physical LEDs per Port        139   374 Table 41: OCP NIC 3.0 Card LED Configuration with Two Physical LEDs per Port        141
373 Table 41: Available Card Functions per Power State        144   375 Table 42: Available Card Functions per Power State        146
374 Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes        146   376 Table 43: Baseboard Power Supply Rail Requirements – Slot Power Envelopes        148
375 Table 43: Power Sequencing Parameters        150   377 Table 44: Power Sequencing Parameters        152
376 Table 44: Digital I/O DC specifications        152   378 Table 45: Digital I/O DC specifications        154
377 Table 45: Digital I/O AC specifications        152   379 Table 46: Digital I/O AC specifications        154
378 Table 46: OCP NIC 3.0 Management Implementation Definitions        153   380 Table 47: OCP NIC 3.0 Management Implementation Definitions        155
379 Table 47: Sideband Management Interface and Transport Requirements        153   381 Table 48: Sideband Management Interface and Transport Requirements        155
380 Table 48: NC-SI Traffic Requirements        154   382 Table 49: NC-SI Traffic Requirements        156
381 Table 49: MC MAC Address Provisioning Requirements        154   383 Table 50: MC MAC Address Provisioning Requirements        156
      384 Table 51: Threshold Severity Level vs Example Threshold Values        159
382 Table 50: Temperature Reporting Requirements        157   385 Table 52: Temperature Reporting Requirements        159
383 Table 51: Power Consumption Reporting Requirements        158   386 Table 53: Power Consumption Reporting Requirements        161
384 Table 52: Pluggable Module Status Reporting Requirements        159   387 Table 54: Pluggable Module Status Reporting Requirements        162
385 Table 53: Management and Pre-OS Firmware Inventory and Update Requirements        159   388 Table 55: Management and Pre-OS Firmware Inventory and Update Requirements        162
386 Table 54: Slot_ID[1:0] to Package ID[2:0] Mapping        161   389 Table 56: Slot_ID[1:0] to Package ID[2:0] Mapping        164
387 Table 55: FRU EEPROM Address Map        162   390 Table 57: FRU EEPROM Address Map        165
388 Table 56: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00        165   391 Table 58: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00        168
389 Table 57: NC-SI over RBT Timing Parameters        171   392 Table 59: NC-SI over RBT Timing Parameters        175
390 Table 58: PCIe Electrical Budgets        175   393 Table 60: PCIe Electrical Budgets        179
391 Table 59: PCIe Test Fixtures for OCP NIC 3.0        176   394 Table 61: PCIe Test Fixtures for OCP NIC 3.0        180
392 Table 60: Hot Aisle Air Temperature Boundary Conditions        179   395 Table 62: Hot Aisle Air Temperature Boundary Conditions        185
393 Table 61: Hot Aisle Airflow Boundary Conditions        179   396 Table 63: Hot Aisle Airflow Boundary Conditions        185
394 Table 62: Cold Aisle Air Temperature Boundary Conditions        179   397 Table 64: Cold Aisle Air Temperature Boundary Conditions        185
395 Table 63: Cold Aisle Airflow Boundary Conditions        180   398 Table 65: Cold Aisle Airflow Boundary Conditions        186
396 Table 64: Reference OCP NIC 3.0 SFF Card Geometry        181   399 Table 66: Reference OCP NIC 3.0 SFF Card Geometry        187
397 Table 65: Reference OCP NIC 3.0 LFF Card Geometry        185   400 Table 67: Reference OCP NIC 3.0 LFF Card Geometry        191
398 Table 66: Card Cooling Tier Definitions (LFM)        198   401 Table 68: Card Cooling Tier Definitions (LFM)        204
399 Table 67: Random Vibration Testing 1.88 GRMS Profile        202   402 Table 69: Random Vibration Testing 1.88 GRMS Profile        208
400 Table 68: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location        206   403 Table 70: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location        212
401 Table 69: Safety Requirements        207   404 Table 71: Safety Requirements        213
402 Table 70: Immunity (ESD) Requirements        207   405 Table 72: Immunity (ESD) Requirements        213
 
412 The OCP NIC Subgroup would like to acknowledge the following member companies for their contributions to the OCP NIC 3.0 specification: <> 415 The OCP NIC Subgroup would like to acknowledge the following member companies for their current contributions to the OCP NIC 3.0 specification:
413 Table 1: Acknowledgements – By Company   416 Table 1: Acknowledgements – Current Contributors – By Company
 
416 Broadcom Limited <> 419 Broadcom Inc.
 
419 Mellanox Technologies, Ltd <> 422 Netronome Systems, Inc.
 
421 Netronome Systems, Inc. <> 424 NVIDIA Mellanox Networking
 
    -+ 611 Conventions
      612 The OCP NIC 3.0 specification adopts the following convention for numerical representations:
      613 Hexadecimal numbers are written with a 0x prefix with the most significant byte first – such as 0xFFFF
      614 Binary numbers are written with a 0b prefix with the most significant bit first – such as 0b0101
      615 Decimal numbers are indicated without any prefix (such as 25)
      616 The unit representations are implemented per the Bureau International des Poids et Mesures (BIPM). The value and unit are separated by a space. The SI symbol and appropriate SI prefix are used (such as 50 °C, 15 A and 200 kΩ).
 
677 The Primary Connector provides all OCP specific management functions as well as up to 16 lanes of PCIe between the OCP NIC and the system motherboard. <> 686 The Primary Connector provides all OCP specific management functions as well as up to 16 lanes of PCIe between the OCP NIC and the system motherboard. The Primary Connector is a 4C+ as defined in SFF-TA-1002 and consists of an OCP Bay for management and sideband signals, and a 4C region.
 
692 Interface Overview (4C Connector): <> 701 Interface Overview (4C region):
 
709 The Secondary Connector provides an additional 16 lanes of PCIe and their respective control signals. <> 718 The Secondary Connector provides an additional 16 lanes of PCIe and their respective control signals. The Secondary Connector is a 4C as defined in SFF-TA-1002.
 
803 On the internal lock variation only, a 5.4 Kg force with a 1 second ramp may be applied to the heatsink during NIC ejection. The mechanical and thermal solution shall be implemented such that the thermal performance is maintained for 10 force cycles (i.e., the NIC still passes all functional tests). If there exists a minimum of (10 mm x 10 mm x 10 mm) of space behind the line side connectors, then each connector shall be able to sustain the same 5.4 Kg force with a 1 second ramp. <> 812 On the internal lock variation only, a 5.4 kg force with a 1 second ramp may be applied to the heatsink during NIC ejection. The mechanical and thermal solution shall be implemented such that the thermal performance is maintained for 10 force cycles (i.e., the NIC still passes all functional tests). If there exists a minimum of (10 mm x 10 mm x 10 mm) of space behind the line side connectors, then each connector shall be able to sustain the same 5.4 kg force with a 1 second ramp.
 
833 Figure 12 illustrates example LFF 3D views of the ejector latch assembly mounted in a chassis utilizing a straddle mount connector and a right angle connector. The baseboard connector options are discussed in Section 3.2. The LFF OCP NIC 3.0 card is identical for both chassis connector options. <> 842 Figure 12 illustrates example LFF 3D views of the ejector latch assembly mounted in a chassis utilizing a straddle mount connector and a right-angle connector. The baseboard connector options are discussed in Section 3.2. The LFF OCP NIC 3.0 card is identical for both chassis connector options.
 
884 The images in Figure 13 illustrate the exploded top level assemblies for both the SFF and the LFF. <> 893 The images in Figure 13 illustrate the exploded top-level assemblies for both the SFF and the LFF.
 
1007 Figure 15 shows the standard SFF I/O bracket with a thumbscrew and pull tab assembly. <> 1016 Figure 15 shows the standard SFF I/O bracket with a thumbscrew and pull-tab assembly.
 
1107 Some NIC vendor(s) may require serial number labels to be placed on the primary side of the PBA. This is permitted but it is up to the NIC vendor(s) to find the appropriate location(s) to affix the label. If a label is to be adhered to the PCB, then the label must be ESD safe as defined by ANSI/ESD S541-2008 (between 104 and 1011 Ohms). <> 1116 Some NIC vendor(s) may require serial number labels to be placed on the primary side of the PBA. This is permitted but it is up to the NIC vendor(s) to find the appropriate location(s) to affix the label. If a label is to be adhered to the PCB, then the label must be ESD safe as defined by ANSI/ESD S541-2008 (between 104 Ω and 1011 Ω).
 
2016 The following offset and height options are available for the right angle Primary and Secondary Connectors. <> 2025 The following offset and height options are available for the right-angle Primary and Secondary Connectors.
 
2952 For baseboards, this signal shall be pulled up to +3.3V_EDGE on the baseboard with a 10 kOhm resistor. This signals shall be connected to the system WAKE# signal. <> 2961 For baseboards, this signal shall be pulled up to +3.3V_EDGE on the baseboard with a 10 kΩ resistor. This signal shall be connected to the system WAKE# signal.
 
2960 This signal shall be pulled up to +3.3V_EDGE on the OCP NIC 3.0 card with 95 kOhm or larger resistance. A baseboard that supports this function must provide a stronger pull up on PWRBRK#. A baseboard pull up value between 4.7 kOhm and 10 kOhm is recommended. The pull up shall meet the TPWRBRK timing parameter as shown in the PCIe CEM Specification. <> 2969 This signal shall be pulled up to +3.3V_EDGE on the OCP NIC 3.0 card with 95 kΩ or larger resistance. A baseboard that supports this function must provide a stronger pull up on PWRBRK#. A baseboard pull up value between 4.7 kΩ and 10 kΩ is recommended. The pull up shall meet the TPWRBRK timing parameter as shown in the PCIe CEM Specification.
 
2966 This section provides the pin assignments for the PCIe present and bifurcation control signals. The AC/DC specifications are defined in Section 3.11. Example connection diagrams are shown in Figure 82 and Figure 83. <> 2975 This section provides the pin assignments for the PCIe present and bifurcation control signals. The AC/DC specifications are defined in Section 3.10.1. Example connection diagrams are shown in Figure 82 and Figure 83.
2967 The PRSNTA#/PRSNTB[0:3]# state shall be used to determine if a card has been physically plugged in. The BIF[0:2]# pins shall be asserted by the baseboard along with the rising edge of AUX_PWR_EN. The BIF[0:2]# pins shall be latched by the OCP NIC 3.0 card when AUX_PWR_EN=1 and NIC_PWR_GOOD=1 to ensure the correct values are detected by the OCP NIC 3.0 card. Changing the pin states after this timing window is not allowed. Refer to the AC timing diagram in Section 3.11 for details.   2976 The PRSNTA#/PRSNTB[0:3]# state shall be used to determine if a card has been physically plugged in. The BIF[0:2]# pins shall be asserted by the baseboard along with the rising edge of AUX_PWR_EN. The BIF[0:2]# pins shall be latched by the OCP NIC 3.0 card when AUX_PWR_EN=1 and NIC_PWR_GOOD=1 to ensure the correct values are detected by the OCP NIC 3.0 card. Changing the pin states after this timing window is not allowed. Refer to the AC timing diagram in Section 3.10.1 for details.
 
2990 For baseboards, these pins shall be connected to the I/O hub and pulled up to +3.3V_EDGE using 1 kOhm resistors. <> 2999 For baseboards, these pins shall be connected to the I/O hub and pulled up to +3.3V_EDGE using 1 kΩ resistors.
2991 For OCP NIC 3.0 cards, these pins shall be strapped to PRSNTA# per the encoding definitions described in Section 3.5.   3000 For OCP NIC 3.0 cards, these pins shall be strapped to PRSNTA# per the encoding definitions described in Section 3.5. The card series resistor values shall be in the range of 0 Ω to ~200 Ω to protect the baseboard logic.
 
3001 For baseboards, the BIF[0:2]# these pins shall be driven from the baseboard I/O hub on the rising edge of AUX_PWR_EN. This allows the baseboard to force the OCP NIC 3.0 card bifurcation. The baseboard may optionally pull the BIF[0:2]# signals to AUX_PWR_EN or to ground per the definitions described in Section 3.5 if no dynamic bifurcation configuration is required. The BIF[0:2]# pins shall be low until AUX_PWR_EN is asserted. <> 3010 For baseboards, the BIF[0:2]# pins shall be driven from the baseboard I/O hub on the rising edge of AUX_PWR_EN. This allows the baseboard to force the OCP NIC 3.0 card bifurcation. The baseboard may optionally pull the BIF[0:2]# signals to AUX_PWR_EN or to ground per the definitions described in Section 3.5 if no dynamic bifurcation configuration is required. The BIF[0:2]# pins shall be low until AUX_PWR_EN is asserted.
 
3050 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to ground through a 100 kOhm pull down resistor. <> 3059 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to ground through a 100 kΩ pull down resistor.
 
3056 For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kOhm pull down resistor on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed. <> 3065 For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed.
3057 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to ground through a 100 kOhm pull down resistor.   3066 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to ground through a 100 kΩ pull down resistor.
 
3065 For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kOhm pull down resistor to GND on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed. <> 3074 For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed.
3066 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to GND through a 100 kOhm pull down.   3075 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to GND through a 100 kΩ pull down.
 
3072 For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kOhm pull down resistor to ground on the baseboard between the RBT isolator and the OCP connector to prevent the card-side signals from floating when the RBT signals are isolated.  <> 3081 For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to ground on the baseboard between the RBT isolator and the OCP connector to prevent the card-side signals from floating when the RBT signals are isolated. 
3073 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to ground through a 100 kOhm pull down.   3082 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to ground through a 100 kΩ pull down.
 
3081 For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kOhm pull down resistor to GND on the baseboard between the RBT isolator and the OCP connector to prevent the card-side signals from floating when the RBT signals are isolated. <> 3090 For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the RBT isolator and the OCP connector to prevent the card-side signals from floating when the RBT signals are isolated.
3082 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to GND through a 100 kOhm pull down.   3091 If the baseboard does not support NC-SI over RBT, then this pin shall be terminated to GND through a 100 kΩ pull down.
3083 Note: Some BMC vendors use the RBT_TXD[0:1] pins as hardware configuration straps. A 4.7 kOhm to 10 kOhm pull up/pull down resistor is permitted between the BMC and the RBT isolator for this purpose. The resulting network will not violate the NC-SI VIHMIN of 2.0V.   3092 Note: Some BMC vendors use the RBT_TXD[0:1] pins as hardware configuration straps. A 4.7 kΩ to 10 kΩ pull up/pull down resistor is permitted between the BMC and the RBT isolator for this purpose. The resulting network will not violate the NC-SI VIHMIN of 2.0V.
 
3105 For baseboards, the SLOT_ID[1:0] pins shall be connected to GND through a 100 Ohm pull down or to +3.3V_EDGE through a 4.7 kOhm pull up. The SLOT[1:0] values are based on the following mapping on a per slot basis: <> 3114 For baseboards, the SLOT_ID[1:0] pins shall be connected to GND through a 100 Ω pull down or to +3.3V_EDGE through a 4.7 kΩ pull up. The SLOT[1:0] values are based on the following mapping on a per slot basis:
 
3122 For OCP NIC 3.0 cards, the SLOT_ID[1:0] pins shall be used to set the RBT Package ID and the FRU EEPROM address on the OCP NIC 3.0 card. The OCP NIC 3.0 card may optionally implement weak pull up or pull down resistors (>47 kOhm) to prevent the silicon pins from floating prior to the local silicon “Aux power good.” <> 3131 For OCP NIC 3.0 cards, the SLOT_ID[1:0] pins shall be used to set the RBT Package ID and the FRU EEPROM address on the OCP NIC 3.0 card. The OCP NIC 3.0 card may optionally implement weak pull up or pull down resistors (>47 kΩ) to prevent the silicon pins from floating prior to the local silicon “Aux power good.”
 
3138 This section provides the pin assignments for the Scan Chain interface signals on the Primary Connector OCP Bay. The scan chain is a point-to-point bus on a per OCP slot basis. The scan chain consists of two unidirectional busses, a common clock and a common load signal. The DATA_OUT signal serially shifts control signals from the baseboard to the OCP NIC 3.0 card. The DATA_IN signal serially shifts bits from the OCP NIC 3.0 card to the baseboard. The DATA_OUT and DATA_IN chains are independent of each other. The scan chain CLK is driven from the baseboard. The LD pin, when asserted by the baseboard, allows loading of the data on to the shift registers. An example timing diagram is shown in Figure 87. An example connection diagram is shown in Figure 88. <> 3147 This section provides the pin assignments for the Scan Chain interface signals on the Primary Connector OCP Bay. The scan chain is a point-to-point bus on a per OCP slot basis. The scan chain consists of two unidirectional busses, a common clock and a common load signal. The DATA_OUT signal serially shifts control signals from the baseboard to the OCP NIC 3.0 card. The DATA_IN signal serially shifts bits from the OCP NIC 3.0 card to the baseboard. The DATA_OUT and DATA_IN chains are independent of each other. The scan chain CLK is driven from the baseboard. The LD pin, when asserted by the baseboard, allows loading of the data on to the shift registers. An example timing diagram is shown in Figure 87. An example connection diagram is shown in Figure 89.
 
3150 For NIC implementations, the CLK pin shall be connected to Shift Registers 0 & 1, and optionally connected to Shift Registers 2 & 3 (if implemented) as defined in the text and Figure 88, below. The CLK pin shall be pulled up to +3.3V_EDGE through a 1 kOhm resistor. <> 3159 For NIC implementations, the CLK pin shall be connected to Shift Registers 0 & 1, and optionally connected to Shift Registers 2 & 3 (if implemented) as defined in the text and Figure 89, below. The CLK pin shall be pulled up to +3.3V_EDGE through a 1 kΩ resistor.
 
3155 For baseboard implementations, the DATA_OUT pin shall be connected to the Primary Connector. The DATA_OUT pin shall be pulled down to GND through a 1 kOhm resistor if the scan chain is not used. <> 3164 For baseboard implementations, the DATA_OUT pin shall be connected to the Primary Connector. The DATA_OUT pin shall be pulled down to GND through a 1 kΩ resistor if the scan chain is not used.
3156 For NIC implementations, the DATA_OUT pin shall be pulled down to GND on the OCP NIC 3.0 card through a 10 kOhm resistor.   3165 For NIC implementations, the DATA_OUT pin shall be pulled down to GND on the OCP NIC 3.0 card through a 10 kΩ resistor.
 
3161 For baseboard implementations, the DATA_IN pin shall be pulled up to +3.3V_EDGE through a 10 kOhm resistor to prevent the input signal from floating if a card is not installed. This pin may be left as a no connect if the scan chain is not used. <> 3170 For baseboard implementations, the DATA_IN pin shall be pulled up to +3.3V_EDGE through a 10 kΩ resistor to prevent the input signal from floating if a card is not installed. This pin may be left as a no connect if the scan chain is not used.
3162 For NIC implementations, the DATA_IN scan chain is required. The DATA_IN pin shall be connected to Shift Register 0, as defined in the text and Figure 88.   3171 For NIC implementations, the DATA_IN scan chain is required. The DATA_IN pin shall be connected to Shift Register 0, as defined in the text and Figure 89.
 
3167 For baseboard implementations, the LD# pin shall be pulled up to +3.3V_EDGE through a 1 kOhm resistor if the scan chain is not used to prevent the OCP NIC 3.0 card from erroneous data latching. <> 3176 For baseboard implementations, the LD# pin shall be pulled up to +3.3V_EDGE through a 1 kΩ resistor if the scan chain is not used to prevent the OCP NIC 3.0 card from erroneous data latching.
3168 For NIC implementations, the LD# pin implementation is required. The LD# pin shall be connected to Shift Registers 0 & 1, and optionally connected to Shift Registers 2 & 3 (if implemented) as defined in the text and Figure 88. The LD# pin shall be pulled up to +3.3V_EDGE through a 10 kOhm resistor.   3177 For NIC implementations, the LD# pin implementation is required. The LD# pin shall be connected to Shift Registers 0 & 1, and optionally connected to Shift Registers 2 & 3 (if implemented) as defined in the text and Figure 89. The LD# pin shall be pulled up to +3.3V_EDGE through a 10 kΩ resistor.
3169 An example Scan Chain timing diagram is shown in Figure 87. The specific timing parameters guaranteed by the Baseboard are shown in Table 28 and timing parameters guaranteed by the OCP NIC 3.0 card are shown in Table 29. The parameters assume operation with a 15pF load between 0°C and 85°C. The values are relaxed when compared to the 74LV165 datasheet and allows system implementers to use alternate implementations (such as a CPLD) instead of discrete logic parts. The data shall be latched by the baseboard on the falling edge of the clock.   3178 Two possible examples for the Scan Chain timing diagram are shown in Figure 87 and Figure 88. The specific timing parameters guaranteed by the Baseboard are shown in Table 28 and timing parameters guaranteed by the OCP NIC 3.0 card are shown in Table 29. The parameters assume operation with a 15 pF load between 0 °C and 85 °C. The values are relaxed when compared to the 74LV165 datasheet and allows system implementers to use alternate implementations (such as a CPLD) instead of discrete logic parts. If the waveform in Figure 87 is implemented, the first DATA_IN bit (bit 7 on Byte 0) shall be sampled before the first rising edge of the clock that follows LD# signal rising edge. If the waveform in Figure 88 is implemented, the first DATA_IN bit shall be latched by the baseboard on the falling edge of the clock. For both examples, each subsequent DATA_IN bit shall be latched by the baseboard on the falling edge of the clock. DATA_OUT shall be driven by the baseboard such that that sufficient setup/hold time is assured to the OCP NIC 3.0 card. Note that the first bit that is shifted on DATA_IN is 0.7 (bit 7 on the least significant Byte) while the first bit that is shifted on DATA_OUT is 3.7 (bit 7 on the most significant Byte).
3170 Figure 87: Example Scan Chain Timing Diagram   3179 Figure 87: Scan Chain Timing Diagram Example 1
      3180 Figure 88: Scan Chain Timing Diagram Example 2
 
3179 15 <> 3189 151
 
    -+ 3197 DATA_OUT valid before CLK↑
 
    -+ 3203 LD# high after CLK↓
      3204 DATA_OUT valid after CLK↑
 
3204 CLK <> 3217 CLK2
 
3208 LD# <> 3221 LD#3
 
    <> 3225 Note 1: When tw< tPD then DATA_IN may only be valid after LD# rising edge.
      3226 Note 2: Applies when LD# is high.
      3227 Note 3: When LD# is low, the CLK signal is ignored by the Scan Chain DATA_IN.
3212 The scan chain provides sideband status indication between the OCP NIC 3.0 card and the baseboard. The scan chain bit definition is defined in the two tables below. The scan chain data stream is 32-bits in length for both the DATA_OUT and the DATA_IN streams. The scan chain implementation is optional on the host, but its implementation is mandatory per Table 30 and Table 31 on all OCP NIC 3.0 cards. The scan chain components operates on the +3.3V_EDGE power domain.   3228 The Scan Chain provides sideband status indication between the OCP NIC 3.0 card and the baseboard. The Scan Chain bit definition is defined in the two tables below. The Scan Chain data stream is 32-bits in length for both the DATA_OUT and the DATA_IN streams. The Scan Chain implementation is optional on the host, but its implementation is mandatory per Table 30 and Table 31 on all OCP NIC 3.0 cards. The Scan Chain components operates on the +3.3V_EDGE power domain.
3213 The DATA_OUT bus is an output from the host. The DATA_OUT bus provides initial configuration options to the OCP NIC 3.0 card. At the time of this writing, the DATA_OUT bus is not used. All baseboard systems that implement the Scan Chain shall connect DATA_OUT between the platform and the Primary Connector for subsequent revisions of this specification. The DATA_OUT data stream shall shift out all 0’s prior to AUX_PWR_EN assertion to prevent leakage paths into unpowered silicon.   3229 The Scan Chain DATA_OUT bus is an output from the host. The Scan Chain DATA_OUT bus provides initial configuration options to the OCP NIC 3.0 card. At the time of this writing, the Scan Chain DATA_OUT bus is not used. All baseboard systems that implement the Scan Chain shall connect DATA_OUT between the platform and the Primary Connector for subsequent revisions of this specification. The DATA_OUT data stream shall shift out all 0’s prior to AUX_PWR_EN assertion to prevent leakage paths into unpowered silicon.
 
3235 The DATA_IN bus is an input to the host and provides NIC status indication. The default implementation is completed with two 8-bit 74LV165 parallel in to serial out shift registers in a cascaded implementation. Up to four shift registers may be implemented to provide additional NIC status indication to the host platform. Alternatively, an OCP NIC 3.0 card vendor may choose to implement this chain using an active device (such as a microcontroller or CPLD). For active device implementations, there is an associated device start-up time. Refer to Section 3.11 for details on the +3.3V_EDGE stable to the first data valid read in ID Mode. <> 3251 The Scan Chain DATA_IN bus is an input to the host and provides NIC status indication. The default implementation is completed with two 8-bit 74LV165 parallel into serial out shift registers in a cascaded implementation. Up to four shift registers may be implemented to provide additional NIC status indication to the host platform. Alternatively, an OCP NIC 3.0 card vendor may choose to implement this chain using an active device (such as a microcontroller or CPLD), as long as it implements the function of the 74LV165, supporting circuitry for the Scan Chain and meets all of the timing specifications given in this specification. For active device implementations, there is an associated device start-up time. Refer to Section 3.10.1 for details on the +3.3V_EDGE stable to the first data valid read in ID Mode.
3236 DATA_IN shift register 0 shall be mandatory for scan chain implementations for the card present, WAKE_N and thermal threshold features. DATA_IN shift registers 1, 2 & 3 are optional depending on the line side I/O and LED fields being reported to the host. Dual port LED applications require shift register 1. Quad port LED applications require shift registers 1 & 2. Octal port applications require shift registers 1, 2 & 3.   3252 The Scan Chain DATA_IN shift register 0 shall be mandatory for scan chain implementations for the card present, WAKE_N and thermal threshold features. Scan Chain DATA_IN shift registers 1, 2 & 3 are optional depending on the line side I/O and LED fields being reported to the host. Dual port LED applications require shift register 1. Quad port LED applications require shift registers 1 & 2. Octal port applications require shift registers 1, 2 & 3.
3237 The host should read the DATA_IN bus multiple times to qualify the incoming data stream. The number of data qualification reads is dependent on the baseboard implementation.   3253 The host should read the Scan Chain DATA_IN bus multiple times to qualify the incoming data stream. The number of data qualification reads is dependent on the baseboard implementation.
3238 On the OCP NIC 3.0 card, a 1 kOhm pull up resistor shall be connected to the SER input of the last DATA_IN shift register. Doing so ensures the default bit value of 0b1 for implementations using less than four shift registers.   3254 On the OCP NIC 3.0 card, a 1 kΩ pull up resistor shall be connected to the SER input of the last DATA_IN shift register. Doing so ensures the default bit value of 0b1 for implementations using less than four shift registers.
 
3263 For LFF designs, this bit shall also serve as the PRSNTB[0]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 88 for details. <> 3279 For LFF designs, this bit shall also serve as the PRSNTB[0]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 89 for details.
 
3271 For LFF designs, this bit shall also serve as the PRSNTB[1]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 88 for details. <> 3287 For LFF designs, this bit shall also serve as the PRSNTB[1]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 89 for details.
 
3279 For LFF designs, this bit shall also serve as the PRSNTB[2]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 88 for details. <> 3295 For LFF designs, this bit shall also serve as the PRSNTB[2]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 89 for details.
 
3287 The FAN_ON_AUX bit shall deassert when the network silicon or transceiver module temperature is at least 5°C below the assertion threshold. <> 3303 The FAN_ON_AUX bit shall deassert when the network silicon or transceiver module temperature is at least 5 °C below the assertion threshold.
 
3291 For LFF designs, this bit shall also serve as the PRSNTB[3]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 88 for details. <> 3307 For LFF designs, this bit shall also serve as the PRSNTB[3]# signal from the Secondary Connector when the card is in ID Mode (AUX_PWR_EN==0). Multiplexing between the two functions shall be controlled via AUX_PWR_EN. Refer to Figure 89 for details.
 
3402 Figure 88: Scan Chain Connection Example <> 3418 Figure 89: Scan Chain Connection Example
 
3405 This section provides the pin assignments for the power supply interface signals. The AC/DC specifications are defined in the PCIe CEM Specification, Rev 4.0 and amended in Section 3.9. An example connection diagram is shown in Figure 89. <> 3421 This section provides the pin assignments for the power supply interface signals. The AC/DC specifications are defined in the PCIe CEM Specification, Rev 4.0 and amended in Section 3.9. An example connection diagram is shown in Figure 90.
 
3433 This signal shall be pulled down to GND through a 10 kOhm resistor on the baseboard. This ensures the OCP NIC 3.0 card power is disabled until instructed to turn on by the baseboard. <> 3449 This signal shall be pulled down to GND through a 10 kΩ resistor on the baseboard. This ensures the OCP NIC 3.0 card power is disabled until instructed to turn on by the baseboard.
 
3437 For OCP NIC 3.0 cards that support the Programming Mode power state, the condition AUX_PWR_EN==0 and MAIN_PWR_EN==1 shall prevent the aux power supplies from being enabled. An example of this logic is shown in Figure 89. <> 3453 For OCP NIC 3.0 cards that support the Programming Mode power state, the condition AUX_PWR_EN==0 and MAIN_PWR_EN==1 shall prevent the aux power supplies from being enabled. An example of this logic is shown in Figure 90.
 
3444 The MAIN_PWR_EN pin is driven by the baseboard and may only be asserted when AUX_PWR_EN is already asserted. The MAIN_PWR_EN pin must be implemented on baseboard systems, but may optionally be used to control main power rail power supplies by the OCP NIC 3.0 card depending on the end point silicon implementation. Depending on the silicon vendor, end point devices may be able to operate in a single power domain, or may require separate power domains to function. <> 3460 The MAIN_PWR_EN pin is driven by the baseboard and may only be asserted when AUX_PWR_EN is already asserted for normal operation in the S0 power state. The MAIN_PWR_EN pin must be implemented on baseboard systems, but may optionally be used to control main power rail power supplies by the OCP NIC 3.0 card depending on the end point silicon implementation. Depending on the silicon vendor, end point devices may be able to operate in a single power domain, or may require separate power domains to function.
3445 For OCP NIC 3.0 cards that support the Programming Mode power state, the condition AUX_PWR_EN == 0 and MAIN_PWR_EN == 1 shall prevent the main power supplies from being enabled. An example of this gating logic is shown in Figure 89.   3461 For OCP NIC 3.0 cards that support the Programming Mode power state, the condition AUX_PWR_EN == 0 and MAIN_PWR_EN == 1 shall prevent the main power supplies from being enabled. An example of this gating logic is shown in Figure 90.
3446 For baseboard implementations, this signal shall be pulled down to GND through a 10 kOhm resistor on the baseboard. This ensures the OCP NIC 3.0 card power is disabled until instructed to turn on by the baseboard.   3462 For baseboard implementations, this signal shall be pulled down to GND through a 10 kΩ resistor on the baseboard. This ensures the OCP NIC 3.0 card power is disabled until instructed to turn on by the baseboard.
 
3455 The truth table shows the expected NIC_PWR_GOOD state for power up sequencing depending on the values of AUX_PWR_EN and MAIN_PWR_EN. <> 3471 The truth table shows the expected NIC_PWR_GOOD state for power up sequencing. This is dependent on the values of AUX_PWR_EN, MAIN_PWR_EN and the enabled power domains operating within design tolerances.
 
3458 NIC_PWR_GOOD Nominal Steady State Value <> 3474 Enabled Power domains nominal
      3475 NIC_PWR_GOOD
 
    -+ 3479 Yes
 
    -+ 3484 Yes
 
    -+ 3489 Yes
 
    -+ 3494 Yes
 
    <> 3497 0
      3498 0
      3499 No
      3500 0
      3501 ID Mode
      3502 1
      3503 0
      3504 No
      3505 0
      3506 Aux Power Mode
      3507 0
      3508 1
      3509 No
      3510 0
      3511 Programming Mode
      3512 1
      3513 1
      3514 No
      3515 0
      3516 Main Power Mode
3476 Refer to the power up and power down sequencing diagrams (Figure 106 and Figure 107) for timing details.   3517 Refer to the power up and power down sequencing diagrams (Figure 107 and Figure 108) for timing details.
3477 Where appropriate, designs that have a separate Main Power domain should also connect to the main power good indication to the NIC_PWR_GOOD signal via a FET to isolate the domains. Refer to Figure 89 for an example implementation.   3518 Where appropriate, designs that have a separate Main Power domain should also connect to the main power good indication to the NIC_PWR_GOOD signal via a FET to isolate the domains. Refer to Figure 90 for an example implementation.
 
3480 For baseboards, this pin may be connected to the platform I/O hub as a NIC power health status indication. This signal shall be pulled down to ground with a 100 kOhm resistor on the baseboard to prevent a false power good indication if no OCP NIC 3.0 card is present. <> 3521 For baseboards, this pin may be connected to the platform I/O hub as a NIC power health status indication. This signal shall be pulled down to ground with a 100 kΩ resistor on the baseboard to prevent a false power good indication if no OCP NIC 3.0 card is present.
 
3483 Figure 89: Example Power Supply Topology <> 3524 Figure 90: Example Power Supply Topology
 
3485 This section provides the pin assignments for the USB 2.0 interface signals. USB 2.0 is only defined for operation on the Primary Connector. USB 2.0 may be used for applications with end point silicon that requires a USB connection to the baseboard. Implementations may also allow for a USB-Serial or USB-JTAG translator for serial or JTAG applications. If multiple USB devices are required, an optional USB hub may be implemented on the OCP NIC 3.0 card. Downstream device discovery is completed as part of the bus enumeration per the USB 2.0 specification. A basic example connection diagram is shown in Figure 90. An example depicting USB-Serial and USB-JTAG connectivity with an USB hub is shown in Figure 91. <> 3526 This section provides the pin assignments for the USB 2.0 interface signals. USB 2.0 is only defined for operation on the Primary Connector. USB 2.0 may be used for applications with end point silicon that requires a USB connection to the baseboard. Implementations may also allow for a USB-Serial or USB-JTAG translator for serial or JTAG applications. If multiple USB devices are required, an optional USB hub may be implemented on the OCP NIC 3.0 card. Downstream device discovery is completed as part of the bus enumeration per the USB 2.0 specification. A basic example connection diagram is shown in Figure 91. An example depicting USB-Serial and USB-JTAG connectivity with an USB hub is shown in Figure 92.
 
3503 Figure 90: USB 2.0 Connection Example – Basic Connectivity <> 3544 Figure 91: USB 2.0 Connection Example – Basic Connectivity
3504 Figure 91: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity   3545 Figure 92: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity
 
3506 This section provides the pin assignments for the UART interface signals. UART is only defined for operation on the Secondary Connector. The UART pins may be used with end point silicon that require console redirection over the baseboard – such as LFF SmartNICs. An example connection diagram is shown in Figure 92. <> 3547 This section provides the pin assignments for the UART interface signals. UART is only defined for operation on the Secondary Connector. The UART pins may be used with end point silicon that require console redirection over the baseboard – such as LFF SmartNICs. An example connection diagram is shown in Figure 93.
 
3526 Figure 92: UART Connection Example <> 3567 Figure 93: UART Connection Example
 
3569 PERST# shall be deasserted >1 s after NIC_PWR_GOOD assertion as defined in Figure 106. Refer to Section 3.11 for timing details. <> 3610 PERST# shall be deasserted >1 s after NIC_PWR_GOOD assertion as defined in Figure 107. Refer to Section 3.10.1 for timing details.
 
3573 Figure 93 illustrates a single host baseboard that supports x16 with a single controller OCP NIC 3.0 card that also supports x16. The PRSTNB[3:0]# state is 0b0111. The BIF[2:0]# state is 0b000 to set the card as a 1x16 for bifurcation capable controllers. For controllers without bifurcation support, the BIF[2:0] pin connections are not required on the card. The PRSNTB encoding notifies the baseboard that this card is only capable of 1 x16. The single host baseboard determines that it is also capable of supporting 1 x16. The resulting link width is 1 x16. <> 3614 Figure 94 illustrates a single host baseboard that supports x16 with a single controller OCP NIC 3.0 card that also supports x16. The PRSTNB[3:0]# state is 0b0111. The BIF[2:0]# state is 0b000 to set the card as a 1x16 for bifurcation capable controllers. For controllers without bifurcation support, the BIF[2:0] pin connections are not required on the card. The PRSNTB encoding notifies the baseboard that this card is only capable of 1 x16. The single host baseboard determines that it is also capable of supporting 1 x16. The resulting link width is 1 x16.
3574 Figure 93: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller)   3615 Figure 94: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller)
 
3577 Figure 94 illustrates a single host baseboard that supports 2 x8 with a dual controller OCP NIC 3.0 card that also supports 2 x8. The PRSTNB[3:0]# state is 0b0110. The BIF[2:0]# state is 0b000 in this example because the network card only supports a 2x8. The PRSNTB encoding notifies the baseboard that this card is only capable of 2 x8. The single host baseboard determines that it is also capable of supporting 2 x8. The resulting link width is 2 x8. <> 3618 Figure 95 illustrates a single host baseboard that supports 2 x8 with a dual controller OCP NIC 3.0 card that also supports 2 x8. The PRSTNB[3:0]# state is 0b0110. The BIF[2:0]# state is 0b000 in this example because the network card only supports a 2x8. The PRSNTB encoding notifies the baseboard that this card is only capable of 2 x8. The single host baseboard determines that it is also capable of supporting 2 x8. The resulting link width is 2 x8.
3578 Figure 94: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)   3619 Figure 95: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)
 
3580 Figure 95 illustrates a quad host baseboard that supports 4 x4 with a single controller OCP NIC 3.0 card that supports 1 x16, 2 x8 and 4 x4. The PRSTNB[3:0]# state is 0b0100. The BIF[2:0]# state in this example is 0b110 as the end point network controller is forced to bifurcate to 4 x4. The PRSNTB encoding notifies the baseboard that this card is only capable of 1 x16, 2 x8 and 4 x4. The quad host baseboard determines that it is also capable of supporting 4 x4. The resulting link width is 4 x4. <> 3621 Figure 96 illustrates a quad host baseboard that supports 4 x4 with a single controller OCP NIC 3.0 card that supports 1 x16, 2 x8 and 4 x4. The PRSTNB[3:0]# state is 0b0100. The BIF[2:0]# state in this example is 0b110 as the end point network controller is forced to bifurcate to 4 x4. The PRSNTB encoding notifies the baseboard that this card is only capable of 1 x16, 2 x8 and 4 x4. The quad host baseboard determines that it is also capable of supporting 4 x4. The resulting link width is 4 x4.
3581 Figure 95: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller)   3622 Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller)
 
3583 Figure 96 illustrates a quad host baseboard that supports 4 x4 with a quad controller OCP NIC 3.0 card that supports 4 x4. The PRSTNB[3:0]# state is 0b0011. The BIF[2:0]# state is a don’t care value as there is no need to instruct the end-point network controllers to a specific bifurcation (each controller only supports 1x4 in this example). The PRSNTB encoding notifies the baseboard that this card is only capable of 4 x4. The quad host baseboard determines that it is also capable of supporting 4 x4. The resulting link width is 4 x4. <> 3624 Figure 97 illustrates a quad host baseboard that supports 4 x4 with a quad controller OCP NIC 3.0 card that supports 4 x4. The PRSTNB[3:0]# state is 0b0011. The BIF[2:0]# state is a don’t care value as there is no need to instruct the end-point network controllers to a specific bifurcation (each controller only supports 1x4 in this example). The PRSNTB encoding notifies the baseboard that this card is only capable of 4 x4. The quad host baseboard determines that it is also capable of supporting 4 x4. The resulting link width is 4 x4.
3584 Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers)   3625 Figure 97: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers)
 
3586 Figure 97 illustrates a single host baseboard that supports 1 x16 with a dual controller OCP NIC 3.0 card that supports 2 x8. The PRSTNB[3:0]# state is 0b0110. The BIF[2:0]# state is 0b000 as each silicon instance only supports 1x8. The PRSNTB encoding notifies the baseboard that this card is only capable of 2 x8. The quad host baseboard determines that it is capable of 1x 16, but down shifts to 1 x8. The resulting link width is 1 x8 and only on endpoint 0. <> 3627 Figure 98 illustrates a single host baseboard that supports 1 x16 with a dual controller OCP NIC 3.0 card that supports 2 x8. The PRSTNB[3:0]# state is 0b0110. The BIF[2:0]# state is 0b000 as each silicon instance only supports 1x8. The PRSNTB encoding notifies the baseboard that this card is only capable of 2 x8. The quad host baseboard determines that it is capable of 1x 16, but down shifts to 1 x8. The resulting link width is 1 x8 and only on endpoint 0.
3587 Figure 97: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)   3628 Figure 98: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers)
 
3662 Figure 98: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links <> 3703 Figure 99: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links
3663 Figure 99: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links   3704 Figure 100: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links
 
3665 Figure 100: SFF PCIe REFCLK Mapping – Quad Host – 4 Links <> 3706 Figure 101: SFF PCIe REFCLK Mapping – Quad Host – 4 Links
 
3669 Figure 101: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links <> 3710 Figure 102: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links
3670 Figure 102: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links   3711 Figure 103: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links
 
3672 Figure 103: LFF PCIe REFCLK Mapping – Quad Host – 4 Links <> 3713 Figure 104: LFF PCIe REFCLK Mapping – Quad Host – 4 Links
 
3682 The numbering of all OCP NIC 3.0 external ports shall start from Port 1. When oriented with the primary side components facing up and viewing directly into the port, Port 1 shall be located on the left hand side. The port numbers shall sequentially increase to the right. Refer to Figure 104 as an example implementation. <> 3723 The numbering of all OCP NIC 3.0 external ports shall start from Port 1. When oriented with the primary side components facing up and viewing directly into the port, Port 1 shall be located on the left hand side. The port numbers shall sequentially increase to the right. Refer to Figure 105 as an example implementation.
 
3734 Figure 104: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement <> 3775 Figure 105: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement
 
3736 Note 1: The example port and LED ordering diagrams shown in Figure 104 are viewed with the card in the horizontal position and the primary side is facing up. <> 3777 Note 1: The example port and LED ordering diagrams shown in Figure 105 are viewed with the card in the horizontal position and the primary side is facing up.
 
3745 There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode (S5), and Main Power Mode (S0). These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 105 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.11. <> 3786 There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode (S5), and Main Power Mode (S0). These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 106 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.10.1.
3746 Figure 105: Baseboard Power States   3787 Figure 106: Baseboard Power States
 
3801 Note 2: The +12V_EDGE rail is on, but the max permissible current draw is up to the ID Mode / Programming Mode current limit defined in Section 3.9. <> 3842 Note 2: The +12V_EDGE rail may be disabled at this time, but the max permissible leakage is up to the ID Mode / Programming Mode current limit defined in Section 3.9. 
 
    <> 3848 In the ID Mode, only +3.3V_EDGE is available for powering up the FRU EEPROM and the Scan Chain devices. All OCP NIC 3.0 cards must enter the ID Mode state for FRU EEPROM and scan chain queries immediately following the NIC Power Off state. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0.
3807 In the ID Mode, only +3.3V_EDGE is available for powering up the FRU EEPROM and the Scan Chain devices. All OCP NIC 3.0 cards must enter the ID Mode state for FRU EEPROM and scan chain queries immediately following the NIC Power Off state. The baseboard queries the EEPROM and determines the OCP NIC 3.0 device capabilities. The FRU EEPROM content requirements are defined in Section 4.10.3. Only the card PRSNTB[0:3]# bits are valid on the scan chain in this mode as the OCP NIC 3.0 card power rails have not yet been enabled via the AUX_PWR_EN and MAIN_PWR_EN signals. The WAKE#, TEMP_WARN#, TEMP_CRIT#, Link and Activity bits are invalid and should be masked by the baseboard in ID Mode.   3849 The baseboard queries the EEPROM and determines the OCP NIC 3.0 device capabilities. The FRU EEPROM content requirements are defined in Section 4.10.3. Only the card PRSNTB[0:3]# bits are valid on the scan chain in this mode as the OCP NIC 3.0 card power rails have not yet been enabled via the AUX_PWR_EN and MAIN_PWR_EN signals. The WAKE#, TEMP_WARN#, TEMP_CRIT#, Link and Activity bits are invalid and should be masked by the baseboard in ID Mode.
3808 The +12V_EDGE rail is not intended to be used in ID Mode, however leakage current may be present. The max leakage is defined in Section 3.9. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0.   3850 Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in ID Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 100 mV (TBD). The bleed resistor on the baseboard shall be 2.2 kΩ (TBD). If +12V_EDGE is present in ID Mode, the max usage is defined in Section 3.9. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0.
 
3810 The Aux Power Mode provides both +3.3V_EDGE as well as +12V_EDGE is available. +12V_EDGE in Aux mode may be used to deliver power to the OCP NIC 3.0 card, but only up to the Aux mode budget as defined in Table 42. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=0, NIC_PWR_GOOD=1 and the duration (TAPL) has passed for the ID-Aux Power Mode ramp. This guarantees the ID mode to Aux Power Mode transition (as shown in Figure 106) has completed and all Aux Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met. <> 3852 The Aux Power Mode provides both +3.3V_EDGE as well as +12V_EDGE is available. +12V_EDGE in Aux mode may be used to deliver power to the OCP NIC 3.0 card, but only up to the Aux mode budget as defined in Table 42. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=0, NIC_PWR_GOOD=1 and the duration (TAPL) has passed for the ID-Aux Power Mode ramp. This guarantees the ID mode to Aux Power Mode transition (as shown in Figure 107) has completed and all Aux Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met.
 
3812 The Main Power Mode provides both +3.3V_EDGE and +12V_EDGE across the OCP connector. The OCP NIC 3.0 card operates in full capacity. Up to 80 W may be delivered on +12V_EDGE for a SFF Card and up to 150 W for a LFF Card. Additionally, up to 3.63 W is delivered on each +3.3V_EDGE pin. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=1, NIC_PWR_GOOD=1 and the duration (TMPL) has passed for the Aux-Main Power Mode ramp. This guarantees the Aux Power Mode to Main Power Mode transition (as shown in Figure 106) has completed and all Main Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met. <> 3854 The Main Power Mode provides both +3.3V_EDGE and +12V_EDGE across the OCP connector. The OCP NIC 3.0 card operates in full capacity. Up to 80 W may be delivered on +12V_EDGE for a SFF Card and up to 150 W for a LFF Card. Additionally, up to 3.63 W is delivered on each +3.3V_EDGE pin. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=1, NIC_PWR_GOOD=1 and the duration (TMPL) has passed for the Aux-Main Power Mode ramp. This guarantees the Aux Power Mode to Main Power Mode transition (as shown in Figure 107) has completed and all Main Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met.
 
3814 The Programming Mode only provides +3.3V_EDGE for powering up the FRU EEPROM. This is an optional state that disables the FRU EEPROM write protection mechanism via combinatorial logic and allows the baseboard to reprogram the FRU EEPROM. This state shall only be entered from ID mode if the FRU EEPROM advertises support for this power state as defined in Section 4.10.3. <> 3856 The Programming Mode provides +3.3V_EDGE for powering up the FRU EEPROM. This is an optional state that disables the FRU EEPROM write protection mechanism via combinatorial logic and allows the baseboard to reprogram the FRU EEPROM. This state shall only be entered from ID mode if the FRU EEPROM advertises support for this power state as defined in Section 4.10.3.
      3857 Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in Programming Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 100 mV (TBD). The bleed resistor on the baseboard shall be 2.2 kΩ (TBD). If +12V_EDGE is present in Programming Mode, the max usage is defined in Section 3.9.
3815 Additionally, the Aux Power Mode and Main Power Mode SVRs need to remain disabled and NIC_PWR_GOOD shall remain low while the card is in this state. An example discrete logic circuit to accomplish this gating is shown in Figure 89. NIC vendors may implement their own gating circuitry as long as the same result is achieved.   3858 Additionally, the Aux Power Mode and Main Power Mode SVRs need to remain disabled and NIC_PWR_GOOD shall remain low while the card is in this state. An example discrete logic circuit to accomplish this gating is shown in Figure 90. NIC vendors may implement their own gating circuitry if the same result is achieved.
 
3818 The baseboard provides +3.3V_EDGE and +12V_EDGE to both the Primary and Secondary Connectors. The rail requirements are leveraged from the PCIe CEM 4.0 specification. For OCP NIC 3.0 implementations, there are five total power envelopes. Four are defined for SFF, and one is defined for LFF. The max current draw is defined in Table 42 for each state and power envelope and is inclusive of the line side transceivers installed on the card. <> 3861 The baseboard provides +3.3V_EDGE and +12V_EDGE to both the Primary and Secondary Connectors. The rail requirements are leveraged from the PCIe CEM 4.0 specification. For OCP NIC 3.0 implementations, there are six total power envelopes. Five are defined for SFF, and one is defined for LFF. The max current draw is defined in Table 42 for each state and power envelope and is inclusive of the line side transceivers installed on the card. The slot power values are the max supportable power delivered to the card for each slot type. This is independent of the +3.3V_EDGE and +12V_EDGE rails deviating from their nominal values.
3819 Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes   3862 Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes
 
3822 Hot Aisle +-    
 
3825 Hot Aisle +-    
 
3827 Hot Aisle <> 3868 50 W Slot SFF
 
3829 Cold Aisle +-    
 
3831 Cold Aisle +-    
 
    -+ 3900 100 mA (max) 100 mA (max)
      3901 1.1 A (max)
      3902 1.1 A (max)
      3903 150 μF (max)
      3904 ±9% (max)
 
3869 ID Mode <> 3913 ID Mode5
3870 Programming Mode   3914 Programming Mode5
 
    -+ 3939 2.1 A (max)
      3940 4.1 A (max)
      3941 1200 μF (max)
      3942 +8/-12% (max)
      3943 50 mA (max)
      3944 50 mA (max)
 
3897 500 μF (max) <> 3947 2000 μF (max)
 
3903 1000 μF (max) <> 3953 2000 μF (max)
 
3906 Note 3: Each OCP NIC 3.0 card shall limit the bulk capacitance to the max values published (500 μF for a SFF card, 1000 μF for a LFF card). <> 3956 Note 3: Each OCP NIC 3.0 card shall limit the bulk capacitance to the max published values.
 
    -+ 3959 Note 5: +12V_EDGE may optionally be disabled during ID Mode and Programming mode. Refer to Section 3.8 for details.
 
3910 Additionally, the baseboard shall advertise its slot power limits to aid in the overall board power budget allocation to prevent a high power card from being enabled in a lower power class slot. This is implemented via the Slot Power Limit Control mechanism as defined in the PCIe Base Specification. The end point silicon will power up in a low power state until power is negotiated. <> 3961 Additionally, the baseboard shall advertise its slot power limits to aid in the overall board power budget allocation to prevent a high-power card from being enabled in a lower power class slot. This is implemented via the Slot Power Limit Control mechanism as defined in the PCIe Base Specification. The end point silicon will power up in a low power state until power is negotiated.
 
3920 Figure 106: Power-Up Sequencing – Normal Operation <> 3971 Figure 107: Power-Up Sequencing – Normal Operation
3921 Figure 107: Power-Down Sequencing – Normal Operation   3972 Figure 108: Power-Down Sequencing – Normal Operation
3922 Figure 108: Programming Mode Sequencing   3973 Figure 109: Programming Mode Sequencing
 
3940 Minimum guaranteed time per spec to spend in ID mode. <> 3991 Minimum time per spec to spend in ID mode.
 
4061 Optional <> 4112 N/A
 
4065 Optional <> 4116 N/A
 
4149 The temperature reporting interface shall be accessible in Aux Power Mode (S5), and Main Power Mode (S0). Table 50 summarizes temperature reporting requirements. These requirements improve the system thermal management and allow the baseboard management device to access key component temperatures on an OCP NIC 3.0 card. When the temperature reporting function is implemented, it is required that the temperature reporting accuracy is within ±3°C. <> 4200 The temperature reporting interface shall be accessible in Aux Power Mode (S5), and Main Power Mode (S0). Table 51 summarizes temperature reporting requirements. These requirements improve the system thermal management and allow the baseboard management device to access key component temperatures on an OCP NIC 3.0 card. When the temperature reporting function is implemented, it is required that the temperature reporting accuracy is within ±3 °C.
      4201 As an example, the assumed hysteresis value for any threshold deassertion is 2 °C. For the three upper severity levels (Warning, Critical and Fatal), the thresholds shall be no less than the reporting accuracy of the temperature sensor (±3 °C) plus the hysteresis value. Therefore, the minimum temperature delta between thresholds should be 5 °C. Larger temperature deltas between severity levels are permitted.
      4202 The Fatal threshold should be set to the temperature at which the silicon may experience permanent failures.
      4203 The Critical threshold should be set to the temperature at which degraded performance or transient errors may occur for the silicon. The life span of the product may be impacted. At minimum, the Critical threshold shall be at least 5 °C below Fatal.
      4204 The Warning threshold should be set to at least 5 °C below Critical and set accordingly to the NIC vendor to give an early indication that the server needs to take remedial action to increase cooling capacity.
      4205 To illustrate this concept, the following example shows a silicon device with an operating Tj of 105 °C per the device datasheet and card temperature reporting accuracy of ±3 °C. The Upper Fatal threshold is fix to the upper device temperature before immediate physical damage is incurred. This threshold values can be adjusted when the card temperature sensor reporting accuracy is better than ±3 °C.
      4206 Table 50: Threshold Severity Level vs Example Threshold Values
      4207 Threshold Severity Level
      4208 Example Threshold Value (°C)
      4209 Upper Fatal
      4210 115
      4211 Upper Critical
      4212 105
      4213 Upper Warning
      4214 100
      4215 For the severity levels above, each baseboard shall ensure the card fatal thermal limit is not exceeded. In ID Mode, baseboard shall determine if the card present in the OCP NIC 3.0 slot is thermally supportable for the thermal tier as defined in the FRU contents. 
4150 Table 50: Temperature Reporting Requirements   4216 Table 51: Temperature Reporting Requirements
 
4189 An OCP NIC 3.0 implementation may be able to report the power consumed at the board level. It is important for the system management that the information about the power consumption can be retrieved over sideband interfaces. Table 51 summarizes the power consumption reporting requirements. <> 4255 An OCP NIC 3.0 implementation may be able to report the power consumed at the board level. It is important for the system management that the information about the power consumption can be retrieved over sideband interfaces. Table 52 summarizes the power consumption reporting requirements.
4190 Table 51: Power Consumption Reporting Requirements   4256 Table 52: Power Consumption Reporting Requirements
 
4212 A pluggable transceiver module is a compact, hot-pluggable transceiver used to connect the OCP 3.0 NIC to an external physical medium. It is important for proper system operation to know the presence and temperature of pluggable transceiver modules. Table 52 summarizes pluggable module status reporting requirements. The transceiver temperature is always reported and is independent of the ASIC die temperature reporting requirements as discussed in Section 4.4. The temperature reporting interface shall be accessible in Aux Power Mode (S5), and Main Power Mode (S0). <> 4278 A pluggable transceiver module is a compact, hot-pluggable transceiver used to connect the OCP 3.0 NIC to an external physical medium. It is important for proper system operation to know the presence and temperature of pluggable transceiver modules. Table 53 summarizes pluggable module status reporting requirements. The transceiver temperature is always reported and is independent of the ASIC die temperature reporting requirements as discussed in Section 4.4. The temperature reporting interface shall be accessible in Aux Power Mode (S5), and Main Power Mode (S0).
4213 Table 52: Pluggable Module Status Reporting Requirements   4279 Table 53: Pluggable Module Status Reporting Requirements
 
4227 An OCP NIC 3.0 implementation can have different types of firmware components for data path, control path, and management path operations. It is desirable that OCP NIC 3.0 implementations support an OS-independent mechanism for the management firmware update. It is desirable that the management firmware update does not require a system reboot for the new firmware image to become active. Table 53 summarizes the firmware inventory and update requirements. <> 4293 An OCP NIC 3.0 implementation can have different types of firmware components for data path, control path, and management path operations. It is desirable that OCP NIC 3.0 implementations support an OS-independent mechanism for the management firmware update. It is desirable that the management firmware update does not require a system reboot for the new firmware image to become active. Table 54 summarizes the firmware inventory and update requirements.
4228 Table 53: Management and Pre-OS Firmware Inventory and Update Requirements   4294 Table 54: Management and Pre-OS Firmware Inventory and Update Requirements
 
4267 Baseboards use the Slot_ID[1:0] values on the Primary Connector for this identification. The value of Slot_ID[1:0] is determined by the encoding shown in Table 54. SLOT_ID[1:0] is statically set high or low on the baseboard and is available on the OCP Bay portion of the Primary Connector. <> 4333 Baseboards use the Slot_ID[1:0] values on the Primary Connector for this identification. The value of Slot_ID[1:0] is determined by the encoding shown in Table 55. SLOT_ID[1:0] is statically set high or low on the baseboard and is available on the OCP Bay portion of the Primary Connector.
4268 Table 54: Slot_ID[1:0] to Package ID[2:0] Mapping   4334 Table 55: Slot_ID[1:0] to Package ID[2:0] Mapping
 
4316 All predefined SMBus addresses for OCP NIC 3.0 are shown in Table 55. Baseboard and OCP NIC 3.0 card designers must ensure additional devices do not conflict. The addresses shown are in 8-bit format and represent the read/write address pair. <> 4382 All predefined SMBus addresses for OCP NIC 3.0 are shown in Table 56. Baseboard and OCP NIC 3.0 card designers must ensure additional devices do not conflict. The addresses shown are in 8-bit format and represent the read/write address pair.
4317 Table 55: FRU EEPROM Address Map   4383 Table 56: FRU EEPROM Address Map
 
4369 The permissible EEPROM addresses are indicated in Table 55. The write/read pair is presented in 8-bit format. The EEPROM shall use double byte addressing and, at minimum, shall be of sufficient size to hold the base FRU contents and any vendor specific information. The double byte write and read accesses are shown in 109 and Figure 110. Refer to the I2C specification for timing details. <> 4435 The permissible EEPROM addresses are indicated in Table 56. The write/read pair is presented in 8-bit format. The EEPROM shall use double byte addressing and, at minimum, shall be of sufficient size to hold the base FRU contents and any vendor specific information. The double byte write and read accesses are shown in 110 and Figure 111. Refer to the I2C specification for timing details.
4370 Figure 109: FRU EEPROM Writes with Double Byte Addressing   4436 Figure 110: FRU EEPROM Writes with Double Byte Addressing
4371 Figure 110: FRU EEPROM Reads with Double Byte Addressing   4437 Figure 111: FRU EEPROM Reads with Double Byte Addressing
 
4374 The FRU update flow is shown in Figure 111. <> 4440 The FRU update flow is shown in Figure 112.
4375 Figure 111: FRU Update Flow   4441 Figure 112: FRU Update Flow
 
4378 The OEM record 0xC0 is used to store specific records for the OCP NIC 3.0 and is stored in the MultiRecord area of the FRU layout. For an OCP NIC 3.0 card, the FRU EEPROM OEM record content based on the format defined in Table 56 shall be populated. <> 4444 The OEM record 0xC0 is used to store specific records for the OCP NIC 3.0 and is stored in the MultiRecord area of the FRU layout. For an OCP NIC 3.0 card, the FRU EEPROM OEM record content based on the format defined in Table 57 shall be populated.
4379 Note: Table 56 only shows a portion of the OEM record. The complete record includes a Common Header and valid record checksum as defined in the IPMI Platform Management FRU Information Storage Definition specification.   4445 Note: Table 57 only shows a portion of the OEM record. The complete record includes a Common Header and valid record checksum as defined in the IPMI Platform Management FRU Information Storage Definition specification.
4380 Table 56: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00   4446 Table 57: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00
 
4391 This field indicates the card OEM Record Version. Baseboards shall read this field to determine the OEM Record format. OCP NIC 3.0 cards compliant to this version of the specification shall be set the field to 0x01. Future changes to the OEM Record format will result in an additional record version value added to this list. <> 4457 This field indicates the card OEM Record Version. Baseboards shall read this field to determine the OEM Record format. OCP NIC 3.0 cards compliant to this version of the specification shall be set the field to 0x01. Future changes to the OEM Record format will result in an additional record version value added to this list.
      4458 0x00 – Reserved0x01 – OCP NIC 3.0 card FRU record released with version 0.90
4392 0x00 – Reserved0x01 – OCP NIC 3.0 card FRU record released with version 0.900x02 – 0xFF – Reserved   4459 0x02 – OCP NIC 3.0 card FRU record released with version 1.10x03 – 0xFF – Reserved
 
4420 Hot aisle standby airflow requirement. <> 4487 Hot aisle standby airflow requirement with Active Cables.
4421 The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode while operating in a hot aisle environment with an approach air temperature of 45°C. Refer to Section 6 for more information about the thermal and environmental requirements.   4488 The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with active cables while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements.
 
4426 Cold aisle standby airflow requirement. <> 4493 Cold aisle standby airflow requirement with Active Cables.
4427 The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode while operating in a cold aisle environment with an approach air temperature of 35°C. Refer to Section 6 for more information about the thermal and environmental requirements.   4494 The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with active cables while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements.
 
4478 SFF-8472 for SFP modules – Power level 1 through 3SFF-8636 for QSFP modules – Power Classes 1 through 7. <> 4545 SFF-8472 for SFP modules – Power level 1 through 3.SFF-8636 for QSFP modules – Power Classes 1 through 8.
4479 0x00 – Passive Cable0x01 – QSFP Active cable Power Class 1 (1.5 W max) / SFP Level 1 (1.0 W max)0x02 – QSFP Active cable Power Class 2 (2.0 W max) / SFP Level 2 (1.5 W max)0x03 – QSFP Active cable Power Class 3 (2.5 W max) / SFP Level 3 (2.0 W max)0x04 – QSFP Active cable Power Class 4 (3.5 W max)0x05 – QSFP Active cable Power Class 5 (4.0 W max)0x06 – QSFP Active cable Power Class 6 (4.5 W max)0x07 – QSFP Active cable Power Class 7 (5.0 W max)0x08 – 0xFE – Reserved0xFF – Unknown   4546 0x00 – Passive Cable0x01 – QSFP Active cable Power Class 1 (1.5 W max) / SFP Level 1 (1.0 W max)0x02 – QSFP Active cable Power Class 2 (2.0 W max) / SFP Level 2 (1.5 W max)0x03 – QSFP Active cable Power Class 3 (2.5 W max) / SFP Level 3 (2.0 W max)0x04 – QSFP Active cable Power Class 4 (3.5 W max)0x05 – QSFP Active cable Power Class 5 (4.0 W max)0x06 – QSFP Active cable Power Class 6 (4.5 W max)0x07 – QSFP Active cable Power Class 7 (5.0 W max)0x08 – QSFP Active cable Power Class 8 (10.0 W max)0x09 – 0xFE – Reserved0xFF – Unknown
 
    <> 4557 24
      4558 1
      4559 Aux Power Supported Ports
      4560 Each bit indicates if the corresponding port can be active in Aux Power Mode. This is a bit map representation. The LSB represents Port 1, the MSB represents Port 8. Refer to Section 3.7.1 for the port numbering nomenclature.
      4561 Examples:0b00000000 – Configuration unknown.0b00000001 – Only Port 1 can be active in Aux Power Mode.0b00000010 – Only Port 2 can be active in Aux Power Mode.0b00000011 – Ports 1 and 2 can be active in Aux Power Mode.Etc.
      4562 25
      4563 2
      4564 Hot aisle standby airflow requirement with Passive Cables or RJ45.
      4565 The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with passive cables or RJ45 while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements.
      4566 Byte 25 is the least significant byte, byte 26 is the most significant byte.
      4567 0x0000-0xFFFE – LFM required for cooling card in Hot Aisle Operation.0xFFFF – Unknown.
      4568 27
      4569 2
      4570 Cold aisle standby airflow requirement with Passive Cables or RJ45.
      4571 The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with passive cables or RJ45 while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements.
      4572 Byte 27 is the least significant byte, byte 28 is the most significant byte.
      4573 0x0000-0xFFFE – LFM required for cooling card in Cold Aisle Operation.0xFFFF – Unknown.
4490 24:30   4574 29:30
4491 7   4575 2
 
4526 The overall end-to-end timing budget is computed by the formula below. The values of each parameter are shown in Table 57 and in DSP0222. The overall BMC pad to ASIC pad timing budget is 3 ns assuming the values shown. This value is inclusive of the RBT isolation buffer on the baseboard, propagation delay through the OCP connector, clock jitter or any clock buffers that may be implemented on the OCP NIC 3.0 card. The addition of these components subtract from the total available budget. <> 4610 The overall end-to-end timing budget is computed by the formula below. The values of each parameter are shown in Table 58 and in DSP0222. The overall BMC pad to ASIC pad timing budget is 3 ns assuming the values shown. This value is inclusive of the RBT isolation buffer on the baseboard, propagation delay through the OCP connector, clock jitter or any clock buffers that may be implemented on the OCP NIC 3.0 card. The addition of these components subtracts from the total available budget.
 
4531 Table 57: NC-SI over RBT Timing Parameters <> 4615 Table 58: NC-SI over RBT Timing Parameters
 
4580 Figure 112: NC-SI over RBT Timing Budget Topology <> 4664 Figure 113: NC-SI over RBT Timing Budget Topology
 
4582 The traces shall be implemented as 50 Ohm ±15% impedance controlled nets. Baseboard and NIC designers are encouraged to follow the guidelines defined in the RMII and NC-SI specifications for physical routing. Refer to Section 3.4.4 and the DSP0222 specification for example interconnect topologies. <> 4666 The traces shall be implemented as 50 Ω ±15% impedance-controlled nets. Baseboard and NIC designers are encouraged to follow the guidelines defined in the RMII and NC-SI specifications for physical routing. Refer to Section 3.4.4 and the DSP0222 specification for example interconnect topologies.
 
4586 The skew requirement defines the max permissible clock skew (TSKEW) between any two system devices. The TSKEW calculation is computed by the formula below. This applies to both the devices on the baseboard and the NIC. L1 is the REF_CLK segment from the baseboard 50 MHz reference clock generator to the BMC. L2 is the REF_CLK segment between the baseboard clock generator to the OCP NIC 3.0 connector and L3 is the segment between the SFF OCP NIC 3.0 card gold fingers and the target ASIC. Refer to Figure 112 for details. The max permissible value of L3 is TNIC,SFF = 900 ps as discussed in Section 5.1.3. Baseboard vendors shall take this value into consideration when analyzing the available timing budget. <> 4670 The skew requirement defines the max permissible clock skew (TSKEW) between any two system devices. The TSKEW calculation is computed by the formula below. This applies to both the devices on the baseboard and the NIC. L1 is the REF_CLK segment from the baseboard 50 MHz reference clock generator to the BMC. L2 is the REF_CLK segment between the baseboard clock generator to the OCP NIC 3.0 connector and L3 is the segment between the SFF OCP NIC 3.0 card gold fingers and the target ASIC. Refer to Figure 113 for details. The max permissible value of L3 is TNIC,SFF = 900 ps as discussed in Section 5.1.3. Baseboard vendors shall take this value into consideration when analyzing the available timing budget.
 
4594 This propagation delay is equivalent to a max length of 5.1 inches assuming standard FR4 material with a propagation delay of 175 ps/in. Additional trace length may be achieved with the use of a higher propagation velocity material (e.g., material with a lower dielectric constant) on the baseboard and OCP NIC 3.0 card or simultaneously using both BMC and ASIC devices with an improved timing from Clock-to-Out (TCO,MAX) value compared to the published value of 12.5 ns in DSP0222. For NIC implementations with clock buffers, the propagation delay of the buffer needs to be included in this timing budget (i.e.,  L3 + TCLK_BUF + L3’ + TCO,MAX + L5 shall be less than 14.3 ns) as shown in Figure 114. <> 4678 This propagation delay is equivalent to a max length of 5.1 inches assuming standard FR4 material with a propagation delay of 175 ps/in. Additional trace length may be achieved with the use of a higher propagation velocity material (e.g., material with a lower dielectric constant) on the baseboard and OCP NIC 3.0 card or simultaneously using both BMC and ASIC devices with an improved timing from Clock-to-Out (TCO,MAX) value compared to the published value of 12.5 ns in DSP0222. For NIC implementations with clock buffers, the propagation delay of the buffer needs to be included in this timing budget (i.e.,  L3 + TCLK_BUF + L3’ + TCO,MAX + L5 shall be less than 14.3 ns) as shown in Figure 115.
4595 If multiple ASICs are utilized, the RBT_CLK_IN signal may be routed with a T-topology as shown in Figure 113. The trace length would be calculated as the delay summation of segment L3 + L3’ for ASIC #0 and L3 + L3” for ASIC #1.  The data path delay to the ASIC is L5.   4679 If multiple ASICs are utilized, the RBT_CLK_IN signal may be routed with a T-topology as shown in Figure 114. The trace length would be calculated as the delay summation of segment L3 + L3’ for ASIC #0 and L3 + L3” for ASIC #1.  The data path delay to the ASIC is L5.
4596 Figure 113: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer   4680 Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer
4597 A clock buffer is optionally permitted if the NIC timing budget is not violated. This is shown in Figure 114. In this case, the trace length would be calculated as the delay summation of trace segment L3 + TCLK_BUF + L3’ for ASIC #0, and L3 + TCLK_BUF + L3’ for ASIC #1.   4681 A clock buffer is optionally permitted if the NIC timing budget is not violated. This is shown in Figure 115. In this case, the trace length would be calculated as the delay summation of trace segment L3 + TCLK_BUF + L3’ for ASIC #0, and L3 + TCLK_BUF + L3’ for ASIC #1.
4598 Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer   4682 Figure 115: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer
 
4606 The OCP NIC 3.0 PCIe channel requirements align with the electrical budget and constraints as detailed in the PCI Express® CEM 4.0 Rev 1.0 and PCI Express Base Specification Rev 4.0. Exceptions or clarifications to the referenced specifications are noted in the sections below. <> 4690 The OCP NIC 3.0 PCIe channel requirements for PCI Express® Gen 4.0 align with the electrical budget and constraints as detailed in the PCI Express® CEM 4.0 Rev 1.0 and PCI Express Base Specification Rev 4.0. Exceptions or clarifications to the referenced specifications are noted in the sections below. The OCP NIC 3.0 PCIe channel requirements for PCI Express® Gen 5.0 differ from the PCI Express® CEM 5.0 Rev 0.7 for Insertion Loss Values as the loss was reduced on the OCP NIC 3.0 to allow the baseboard additional margin for SFF implementations. The OCP NIC 3.0 LFF aligns with the specification. Refer to Section 5.3.1.2 for details.
 
4608 REFCLK requirements are detailed in the PCI Express CEM 4.0 Rev 1.0 Section 2.1. <> 4692 REFCLK requirements are detailed in the PCI Express CEM 5.0 Rev 0.7 Section 2.1.
 
4611 Table 58: PCIe Electrical Budgets <> 4695 Table 59: PCIe Electrical Budgets
 
    -+ 4698 PCIe CEM 5.0 Rev 0.7 Specification Section
 
    -+ 4701 PCIe Base Specification 5.0 Section 8.3.9 Symbol CTX
 
    -+ 4705 Section 4.7.2 and Appendix A.
      4706 -7.0 dB at 16 GHz for SFF1
      4707 Section 4.7.11 for LFF
 
4621 Also refer to the PCIe Base Specification Section 8.3.5 <> 4710 Also refer to the PCIe Base Specification 4.0 Section 8.3.5
      4711 Section 4.7.3 for 8 GT/s, 16 GT/s and 32 GT/s.
      4712 Also refer to the PCIe Base Specification 5.0 Section 8.3.5
 
    -+ 4715 Section 4.7.4
 
    -+ 4718 Section 4.7.5
 
    -+ 4721 Section 4.7.6 and PCIe Base Spec Chapter 9
 
    -+ 4724 Section 4.7.7
 
    -+ 4727 Section 4.7.8
 
    -+ 4730 Section 4.7.9
      4731 Note 1: OCP NIC 3.0 SFF deviates from the PCIe CEM specification on Insertion Loss Values at PCIe Gen5 speeds (32GT/s only).
 
4639 For PCIe transmit and receive differential pairs, the target impedance is 85 Ohms ±10%. <> 4737 For PCIe transmit and receive differential pairs, the target impedance is 85 Ω ±10%.
4640 For the PCIe REFCLKs, the target impedance is 100 Ohms ±10%.   4738 For the PCIe REFCLKs, the target impedance is 100 Ω ±10%.
 
4642 Test Fixtures are designed using the PCIe CEM 4.0 CLB and CBB. The fixtures host interface has been modified to the OCP connector standard and there are two version of the fixtures, one for Gen 3 PCIe and one for Gen 4 PCIe. Careful attention has been placed on these fixtures to help insure that standard test equipment automation should work without significant modification. <> 4740 Test Fixtures are designed using the PCIe CEM CLB and CBB. The fixtures host interface has been modified to the OCP connector standard and there are three versions of the fixtures for both the SFF and LFF OCP NIC 3.0 cards for Gen 3, Gen 4 and Gen 5 PCIe rates. Careful attention has been placed on these fixtures to help ensure that standard test equipment automation should work without significant modification. PCIe Gen 5 automation scripts may need to be modified as the OCP NIC 3.0 insertion loss budget differs from the PCIe CEM 5.0 32GT/s values.
4643 Table 59: PCIe Test Fixtures for OCP NIC 3.0   4741 Table 60: PCIe Test Fixtures for OCP NIC 3.0
 
    -+ 4750 Gen 5
      4751 TBD
 
    -+ 4757 Gen 5
      4758 TBD
 
4658 Figure 115: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF <> 4760 Figure 116: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF
 
4660 Figure 116: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF <> 4762 Figure 117: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF
 
    -+ 4765 For PCIe Gen 5.0, OCP NIC 3.0 modifies the insertion loss budget on the SFF as shown in Table 59 and the test methodology may need to be adjusted to compensate for this difference. The electrical interface may be tested against the PCI Express® Architecture PHY Test Specification Revision 5.0, providing that the appropriate test fixtures from Section 5.3.2 are used and the insertion loss difference is compensated.
 
4673 The airflow in typical server systems will approach from the card edge or heatsink side of the card. This airflow direction is referred to as Hot Aisle cooling and is illustrated below in Figure 117. The term Hot Aisle refers to the card being located at the rear of the system where the local inlet airflow is preheated by the upstream system components (e.g., HDD, CPU, DIMM, etc.). <> 4776 The airflow in typical server systems will approach from the card edge or heatsink side of the card. This airflow direction is referred to as Hot Aisle cooling and is illustrated below in Figure 118. The term Hot Aisle refers to the card being located at the rear of the system where the local inlet airflow is preheated by the upstream system components (e.g., HDD, CPU, DIMM, etc.).
4674 Figure 117: Airflow Direction for Hot Aisle Cooling (SFF and LFF)   4777 Figure 118: Airflow Direction for Hot Aisle Cooling (SFF and LFF)
4675 The boundary conditions for Hot Aisle cooling are shown below in Table 60 and Table 61. The low temperature is listed at 5°C and assumes fresh air could be ducted to the back of the system from the front. More typically the inlet temperature to the OCP NIC 3.0 card will be in the same range as PCIe cards located at the back of the system (55°C local inlet temperature). Depending on the system design, power density, and airflow the inlet temperature to the OCP NIC 3.0 card may be as high as 60°C or 65°C. The airflow velocities listed in Table 61 represent the airflow velocities typical in mainstream servers. Higher airflow velocities are available within the Hot Aisle cooling tiers listed in Table 66 but card designers must be sure to understand the system level implications of such high card LFM requirements.   4778 The boundary conditions for Hot Aisle cooling are shown below in Table 61 and Table 62. The low temperature is listed at 5 °C and assumes fresh air could be ducted to the back of the system from the front. More typically the inlet temperature to the OCP NIC 3.0 card will be in the same range as PCIe cards located at the back of the system (55 °C local inlet temperature). Depending on the system design, power density, and airflow the inlet temperature to the OCP NIC 3.0 card may be as high as 60 °C or 65 °C. The airflow velocities listed in Table 62 represent the airflow velocities typical in mainstream servers. Higher airflow velocities are available within the Hot Aisle cooling tiers listed in Table 67 but card designers must be sure to understand the system level implications of such high card LFM requirements.
 
4677 Table 60: Hot Aisle Air Temperature Boundary Conditions <> 4780 Table 61: Hot Aisle Air Temperature Boundary Conditions
 
4683 5ׄ°C <> 4786 5 °C
 
4685 55°C <> 4788 55 °C
4686 60°C   4789 60 °C
4687 65°C   4790 65 °C
 
4689 Table 61: Hot Aisle Airflow Boundary Conditions <> 4792 Table 62: Hot Aisle Airflow Boundary Conditions
 
4700 When installed in the front of a server the airflow will approach from the I/O connector (e.g., SFP, QSFP or RJ45) side of the card. This airflow direction is referred to as Cold Aisle cooling and is illustrated below in Figure 118. The term Cold Aisle refers to the card being located at the front of the system where the local inlet airflow is assumed to be the same temperature as the system inlet airflow. <> 4803 When installed in the front of a server the airflow will approach from the I/O connector (e.g., SFP, QSFP or RJ45) side of the card. This airflow direction is referred to as Cold Aisle cooling and is illustrated below in Figure 119. The term Cold Aisle refers to the card being located at the front of the system where the local inlet airflow is assumed to be the same temperature as the system inlet airflow.
4701 Figure 118: Airflow Direction for Cold Aisle Cooling (SFF and LFF)   4804 Figure 119: Airflow Direction for Cold Aisle Cooling (SFF and LFF)
4702 The boundary conditions for Cold Aisle cooling are shown below in Table 62 and Table 63. The temperature values listed in Table 62 assume the inlet temperature to the OCP NIC 3.0 card to be the same as the system inlet. The low, typical, high, and max temperatures listed align with the ASHRAE A1, A2, A3, and A4 environmental classes. Depending on the system, the supported ASHRAE class may limit the maximum temperature to the OCP 3.0 NIC card. However, for more broad industry support, cards should be designed to the upper end of the ASHRAE classes (e.g., class A4).   4805 The boundary conditions for Cold Aisle cooling are shown below in Table 63 and Table 64. The temperature values listed in Table 63 assume the inlet temperature to the OCP NIC 3.0 card to be the same as the system inlet. The low, typical, high, and max temperatures listed align with the ASHRAE A1, A2, A3, and A4 environmental classes. Depending on the system, the supported ASHRAE class may limit the maximum temperature to the OCP 3.0 NIC card. However, for more broad industry support, cards should be designed to the upper end of the ASHRAE classes (e.g., class A4).
4703 Table 62: Cold Aisle Air Temperature Boundary Conditions   4806 Table 63: Cold Aisle Air Temperature Boundary Conditions
 
4709 5°C <> 4812 5 °C
4710 25-35°C   4813 25-35 °C
 
4712 40°C <> 4815 40 °C
 
4714 45°C <> 4817 45 °C
 
4716 Table 63: Cold Aisle Airflow Boundary Conditions <> 4819 Table 64: Cold Aisle Airflow Boundary Conditions
 
4729 The ASIC or controller chip is typically the highest power component on the card. Thus, as OCP NIC 3.0 cards are developed it is important to understand the ASIC cooling capability. Figure 119 below provides an estimate of the maximum ASIC power that can be supported as a function of the local inlet velocity for the SFF card in a hot aisle cooling configuration. Each curve in Figure 119 represents a different local inlet air temperature from 45°C to 65°C. <> 4832 The ASIC or controller chip is typically the highest power component on the card. Thus, as OCP NIC 3.0 cards are developed it is important to understand the ASIC cooling capability. Figure 120 below provides an estimate of the maximum ASIC power that can be supported as a function of the local inlet velocity for the SFF card in a hot aisle cooling configuration. Each curve in Figure 120 represents a different local inlet air temperature from 45 °C to 65 °C.
4730 Figure 119: ASIC Supportable Power for Hot Aisle Cooling – SFF   4833 Figure 120: ASIC Supportable Power for Hot Aisle Cooling – SFF
4731 The curves shown in Figure 119 were obtained using CFD analysis of a reference OCP NIC 3.0 SFF card. The reference card has a 20 mm x 20 mm ASIC with two QSFP connectors. Figure 120 shows a comparison of the 3D CAD and CFD model geometry for the reference OCP NIC 3.0 card. Additional card geometry parameters and boundary conditions used in the reference CFD analysis are summarized in Table 64. The OCP NIC 3.0 simulation was conducted within a virtual version of the test fixture defined in Section 6.4.   4834 The curves shown in Figure 120 were obtained using CFD analysis of a reference OCP NIC 3.0 SFF card. The reference card has a 20 mm x 20 mm ASIC with two QSFP connectors. Figure 121 shows a comparison of the 3D CAD and CFD model geometry for the reference OCP NIC 3.0 card. Additional card geometry parameters and boundary conditions used in the reference CFD analysis are summarized in Table 65. The OCP NIC 3.0 simulation was conducted within a virtual version of the test fixture defined in Section 6.4.
4732 Figure 120: OCP NIC 3.0 SFF Reference Design and CFD Geometry   4835 Figure 121: OCP NIC 3.0 SFF Reference Design and CFD Geometry
4733 Table 64: Reference OCP NIC 3.0 SFF Card Geometry   4836 Table 65: Reference OCP NIC 3.0 SFF Card Geometry
 
4763 95°C <> 4866 95 °C
 
4766 An increase in the supported ASIC power or a decrease in the required airflow velocity may be achieved through heatsink size and material changes. For example, a larger heatsink or a heatsink made out of copper could improve ASIC cooling and effectively shift up the supportable power curves shown in Figure 119. <> 4869 An increase in the supported ASIC power or a decrease in the required airflow velocity may be achieved through heatsink size and material changes. For example, a larger heatsink or a heatsink made out of copper could improve ASIC cooling and effectively shift up the supportable power curves shown in Figure 120.
4767 It is important to point out that the curves shown in Figure 119 represent only the maximum ASIC power that can be supported vs. the supplied inlet velocity. Other heat loads on the card may require airflow velocities above and beyond that required to cool the ASIC. SFP or QSFP optical transceivers located downstream of the AISC will in many cases pose a greater cooling challenge than the ASIC cooling. Cooling the optical transceivers becomes even more difficult as the ASIC power is increased due to additional preheating of the air as it moves through the ASIC heatsink. OCP NIC 3.0 designers must consider all heat sources early in the design process to ensure the card thermal solution is sufficient for the feature set. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3.   4870 It is important to point out that the curves shown in Figure 120 represent only the maximum ASIC power that can be supported vs. the supplied inlet velocity. Other heat loads on the card may require airflow velocities above and beyond that required to cool the ASIC. SFP or QSFP optical transceivers located downstream of the AISC will in many cases pose a greater cooling challenge than the ASIC cooling. Cooling the optical transceivers becomes even more difficult as the ASIC power is increased due to additional preheating of the air as it moves through the ASIC heatsink. OCP NIC 3.0 designers must consider all heat sources early in the design process to ensure the card thermal solution is sufficient for the feature set. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3.
4768 Card designers must also consider the airflow capability of the server systems that the cards are targeted for use within. Figure 121 below shows the SFF ASIC supportable power curves with an overlay of three server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions.   4871 Card designers must also consider the airflow capability of the server systems that the cards are targeted for use within. Figure 122 below shows the SFF ASIC supportable power curves with an overlay of three server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions.
4769 Figure 121: Server System Airflow Capability – SFF Card Hot Aisle Cooling   4872 Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling
 
4771 The NIC vendor shall provide the required LFM during S5 state in the FRU EEPROM (see Section 4.10.3). The cold aisle should be tested at 35°C; the hot aisle should be tested at 45°C. <> 4874 The NIC vendor shall provide the required LFM during S5 state in the FRU EEPROM (see Section 4.10.3). The cold aisle should be tested at 35 °C; the hot aisle should be tested at 45 °C.
4772 Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode   4875 Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode
 
4774 Figure 123 below provides an estimate of the maximum ASIC power that can be supported as a function of the local inlet velocity for the LFF card in a hot aisle cooling configuration. Each curve in Figure 123 represents a different local inlet air temperature from 45°C to 65°C. <> 4877 Figure 124 below provides an estimate of the maximum ASIC power that can be supported as a function of the local inlet velocity for the LFF card in a hot aisle cooling configuration. Each curve in Figure 124 represents a different local inlet air temperature from 45 °C to 65 °C.
4775 Figure 123: ASIC Supportable Power for Hot Aisle Cooling – LFF Card   4878 Figure 124: ASIC Supportable Power for Hot Aisle Cooling – LFF Card
4776 The curves shown in Figure 123 were obtained using CFD analysis of the reference OCP NIC 3.0 LFF card. The reference card has a 45 mm x 45 mm ASIC with two QSFP connectors. Additional card geometry parameters and boundary conditions used in the reference CFD analysis are summarized in Table 65. Figure 124 shows a comparison of the 3D CAD and CFD model geometry for the reference OCP NIC 3.0 card.   4879 The curves shown in Figure 124 were obtained using CFD analysis of the reference OCP NIC 3.0 LFF card. The reference card has a 45 mm x 45 mm ASIC with two QSFP connectors. Additional card geometry parameters and boundary conditions used in the reference CFD analysis are summarized in Table 66. Figure 125 shows a comparison of the 3D CAD and CFD model geometry for the reference OCP NIC 3.0 card.
4777 Figure 124: OCP NIC 3.0 LFF Reference Design and CFD Geometry   4880 Figure 125: OCP NIC 3.0 LFF Reference Design and CFD Geometry
4778 Table 65: Reference OCP NIC 3.0 LFF Card Geometry   4881 Table 66: Reference OCP NIC 3.0 LFF Card Geometry
 
4808 95°C <> 4911 95 °C
 
4812 Figure 125 below shows the LFF ASIC supportable power curves with an overlay of three server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions. <> 4915 Figure 126 below shows the LFF ASIC supportable power curves with an overlay of three server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions.
4813 Figure 125: Server System Airflow Capability – LFF Card Hot Aisle Cooling   4916 Figure 126: Server System Airflow Capability – LFF Card Hot Aisle Cooling
 
4816 The ASIC cooling analysis for the SFF Card in the Cold Aisle configuration was conducted utilizing the same geometry and boundary conditions described in Figure 120 and Table 64 with airflow moving from I/O connector to ASIC (opposite to the Hot Aisle analysis). Figure 126 below shows the results of this analysis for the Cold Aisle cooling configuration. Each curve in Figure 126 represents a different system inlet air temperature from 25°C to 45°C. <> 4919 The ASIC cooling analysis for the SFF Card in the Cold Aisle configuration was conducted utilizing the same geometry and boundary conditions described in Figure 121 and Table 65 with airflow moving from I/O connector to ASIC (opposite to the Hot Aisle analysis). Figure 127 below shows the results of this analysis for the Cold Aisle cooling configuration. Each curve in Figure 127 represents a different system inlet air temperature from 25 °C to 45 °C.
 
4818 Figure 126: ASIC Supportable Power for Cold Aisle Cooling – SFF Card <> 4921 Figure 127: ASIC Supportable Power for Cold Aisle Cooling – SFF Card
4819 Similar to Figure 121 for Hot Aisle cooling, Figure 127 below shows the ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling.   4922 Similar to Figure 122 for Hot Aisle cooling, Figure 128 below shows the ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling.
4820 Figure 127: Server System Airflow Capability – SFF Cold Aisle Cooling   4923 Figure 128: Server System Airflow Capability – SFF Cold Aisle Cooling
4821 A comparison of Hot Aisle (55°C) and Cold Aisle (35°C) SFF ASIC cooling capability curves is shown below in Figure 128. The comparison shows the Hot Aisle ASIC cooling capability at 12 W at 150 LFM while the cold Aisle cooling capability shows support for 19 W at 150 LFM. In general, based on the reference geometry, the Cold Aisle cooling configuration allows for higher supported ASIC power at lower velocities due primarily to the lower inlet temperatures local to the OCP NIC 3.0 card when in the Cold Aisle cooling configuration.   4924 A comparison of Hot Aisle (55 °C) and Cold Aisle (35 °C) SFF ASIC cooling capability curves is shown below in Figure 129. The comparison shows the Hot Aisle ASIC cooling capability at 12 W at 150 LFM while the cold Aisle cooling capability shows support for 19 W at 150 LFM. In general, based on the reference geometry, the Cold Aisle cooling configuration allows for higher supported ASIC power at lower velocities due primarily to the lower inlet temperatures local to the OCP NIC 3.0 card when in the Cold Aisle cooling configuration.
4822 Figure 128: ASIC Supportable Power Comparison – SFF Card   4925 Figure 129: ASIC Supportable Power Comparison – SFF Card
 
4824 The ASIC cooling analysis for the LFF card in Cold Aisle configuration was conducted utilizing the same geometry and boundary conditions described in Figure 124 and Table 65 with airflow moving from I/O connector to ASIC (opposite to the Hot Aisle analysis). Figure 129 below shows the results of this analysis for the Cold Aisle cooling configuration. Each curve in Figure 129 represents a different system inlet air temperature from 25°C to 45°C. <> 4927 The ASIC cooling analysis for the LFF card in Cold Aisle configuration was conducted utilizing the same geometry and boundary conditions described in Figure 125 and Table 66 with airflow moving from I/O connector to ASIC (opposite to the Hot Aisle analysis). Figure 130 below shows the results of this analysis for the Cold Aisle cooling configuration. Each curve in Figure 130 represents a different system inlet air temperature from 25 °C to 45 °C.
4825 Figure 129: ASIC Supportable Power for Cold Aisle Cooling – LFF Card   4928 Figure 130: ASIC Supportable Power for Cold Aisle Cooling – LFF Card
4826 Similar to Figure 127 for LFF Hot Aisle cooling, Figure 130 below shows the LFF ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling.   4929 Similar to Figure 128 for LFF Hot Aisle cooling, Figure 131 below shows the LFF ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling.
4827 Figure 130: Server System Airflow Capability – LFF Cold Aisle Cooling   4930 Figure 131: Server System Airflow Capability – LFF Cold Aisle Cooling
4828 A comparison of Hot Aisle (55°C) and Cold Aisle (35°C) LFF ASIC cooling capability curves is shown below in Figure 131. The comparison shows the Hot Aisle ASIC cooling capability at 19 W at 150 LFM while the cold Aisle cooling capability shows support for 42 W at 150 LFM. In general, based on the reference geometry, the Cold Aisle cooling configuration allows for higher supported ASIC power at lower velocities due primarily to the lower inlet temperatures local to the OCP NIC 3.0 card when in the Cold Aisle cooling configuration.   4931 A comparison of Hot Aisle (55 °C) and Cold Aisle (35 °C) LFF ASIC cooling capability curves is shown below in Figure 132. The comparison shows the Hot Aisle ASIC cooling capability at 19 W at 150 LFM while the cold Aisle cooling capability shows support for 42 W at 150 LFM. In general, based on the reference geometry, the Cold Aisle cooling configuration allows for higher supported ASIC power at lower velocities due primarily to the lower inlet temperatures local to the OCP NIC 3.0 card when in the Cold Aisle cooling configuration.
4829 Figure 131: ASIC Supportable Power Comparison – LFF Card   4932 Figure 132: ASIC Supportable Power Comparison – LFF Card
 
4849 Predefined locations for fixture airflow/temperature sensors on fixture PCB silkscreen. Quantity 3x per SFF board and quantity 4x for LFF – see Figure 137 <> 4952 Predefined locations for fixture airflow/temperature sensors on fixture PCB silkscreen. Quantity 3x per SFF board and quantity 4x for LFF – see Figure 138
 
4856 Images of the SFF thermal test fixture are shown in Figure 132 and Figure 133. The SFF fixture PCB is shown in Figure 134. Note the three candlestick sensor locations directly next to the OCP NIC 3.0 connectors. <> 4959 Images of the SFF thermal test fixture are shown in Figure 133 and Figure 134. The SFF fixture PCB is shown in Figure 135. Note the three candlestick sensor locations directly next to the OCP NIC 3.0 connectors.
4857 Figure 132: SFF Thermal Test Fixture Preliminary Design   4960 Figure 133: SFF Thermal Test Fixture Preliminary Design
4858 Figure 133: SFF Thermal Test Fixture Preliminary Design – Cover Removed   4961 Figure 134: SFF Thermal Test Fixture Preliminary Design – Cover Removed
4859 Figure 134: SFF Card Thermal Test Fixture PCB   4962 Figure 135: SFF Card Thermal Test Fixture PCB
 
4861 Images of the LFF thermal test fixture are shown in Figure 135 and Figure 136. The LFF fixture PCB is shown in Figure 137. Note the three candlestick sensor locations directly next to the OCP NIC 3.0 connectors. <> 4964 Images of the LFF thermal test fixture are shown in Figure 136 and Figure 137. The LFF fixture PCB is shown in Figure 138. Note the three candlestick sensor locations directly next to the OCP NIC 3.0 connectors.
4862 Figure 135: LFF Card Thermal Test Fixture Design   4965 Figure 136: LFF Card Thermal Test Fixture Design
 
4864 Figure 136: LFF Card Thermal Test Fixture Design – Cover Removed <> 4967 Figure 137: LFF Card Thermal Test Fixture Design – Cover Removed
4865 Figure 137: LFF Card Thermal Test Fixture PCB   4968 Figure 138: LFF Card Thermal Test Fixture PCB
 
4867 When utilizing the OCP NIC 3.0 thermal test fixture, the wind tunnel or flow bench must be configured to push airflow for Hot Aisle cooling or to pull airflow for Cold Aisle cooling as shown in Figure 138. <> 4970 When utilizing the OCP NIC 3.0 thermal test fixture, the wind tunnel or flow bench must be configured to push airflow for Hot Aisle cooling or to pull airflow for Cold Aisle cooling as shown in Figure 139.
4868 Figure 138: Thermal Test Fixture Airflow Direction   4971 Figure 139: Thermal Test Fixture Airflow Direction
 
4871 Figure 139 and Figure 140 below show the air velocity at each sensor location vs. the total fixture flow rate in CFM. The curves shown in these figures are based on the data collected from the CFD models discussed in Section 6.3. Note the error between the velocities obtained from the sensor locations vs. the velocity based on the duct cross-sectional area. <> 4974 Figure 140 and Figure 141 below show the air velocity at each sensor location vs. the total fixture flow rate in CFM. The curves shown in these figures are based on the data collected from the CFD models discussed in Section 6.3. Note the error between the velocities obtained from the sensor locations vs. the velocity based on the duct cross-sectional area.
4872 Figure 139: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow   4975 Figure 140: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow
4873 Figure 140: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow   4976 Figure 141: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow
 
4879 Card Cooling Tiers for Hot and Cold Aisle Cooling configurations are defined in Table 66. The values in the table are listed with units shown in LFM. Future releases of this specification will provide more detail to the Card Cooling Tier curve definition. <> 4982 Card Cooling Tiers for Hot and Cold Aisle Cooling configurations are defined in Table 67. The values in the table are listed with units shown in LFM. Future releases of this specification will provide more detail to the Card Cooling Tier curve definition.
4880 Table 66: Card Cooling Tier Definitions (LFM)   4983 Table 67: Card Cooling Tier Definitions (LFM)
4881 A graphical view of the Card Cooling Tiers is shown in Figure 141. The Tiers range from 0 LFM to as high as 1000 LFM at 55°C local inlet temperature. It is important to understand that the cooling tiers extend well beyond the airflow range of most server systems. As noted in Section 6.2, card designers must consider the airflow capability of the systems that the cards are to be used in when designing the card thermal solution and component placement. Figure 142 and Figure 143 below show the range of typical system capability for Hot Aisle and Cold Aisle configurations. Cards designed to these typical ranges (Tiers 1-6) will be low risk to support in most if not all server systems. Alternatively, cards that require Tier 7 or greater may still work in many server systems but may require extra validation testing, specific system slot location requirements, and potentially ambient temperature and hardware restrictions.   4984 A graphical view of the Card Cooling Tiers is shown in Figure 142. The Tiers range from 0 LFM to as high as 1000 LFM at 55 °C local inlet temperature. It is important to understand that the cooling tiers extend well beyond the airflow range of most server systems. As noted in Section 6.2, card designers must consider the airflow capability of the systems that the cards are to be used in when designing the card thermal solution and component placement. Figure 143 and Figure 144 below show the range of typical system capability for Hot Aisle and Cold Aisle configurations. Cards designed to these typical ranges (Tiers 1-6) will be low risk to support in most if not all server systems. Alternatively, cards that require Tier 7 or greater may still work in many server systems but may require extra validation testing, specific system slot location requirements, and potentially ambient temperature and hardware restrictions.
4882 Figure 141: Graphical View of Card Cooling Tiers   4985 Figure 142: Graphical View of Card Cooling Tiers
4883 Figure 142: Typical Operating Range for Hot Aisle Configurations   4986 Figure 143: Typical Operating Range for Hot Aisle Configurations
4884 Figure 143: Typical Operating Range for Cold Aisle Configurations   4987 Figure 144: Typical Operating Range for Cold Aisle Configurations
 
4890 The fixture is comprised of a universal baseplate that allows for attaching SFF or LFF rail guides and simulated chassis faceplates. The baseplate includes an industry standard vibration table hole pattern for securing the UUT for test. Figure 144 and Figure 145 show the SFF and LFF fixtures, respectively. <> 4993 The fixture is comprised of a universal baseplate that allows for attaching SFF or LFF rail guides and simulated chassis faceplates. The baseplate includes an industry standard vibration table hole pattern for securing the UUT for test. Figure 145 and Figure 146 show the SFF and LFF fixtures, respectively.
 
4892 Figure 144: SFF Shock and Vibe Fixture <> 4995 Figure 145: SFF Shock and Vibe Fixture
4893 Figure 145: LFF Shock and Vibe Fixture   4996 Figure 146: LFF Shock and Vibe Fixture
 
4900 Non-operational vibration testing is performed at 1.88 GRMS for a duration of 15 minutes per side per Table 67. <> 5003 Non-operational vibration testing is performed at 1.88 GRMS for a duration of 15 minutes per side per Table 68.
4901 Table 67: Random Vibration Testing 1.88 GRMS Profile   5004 Table 68: Random Vibration Testing 1.88 GRMS Profile
 
4930 Figure 146: Dye and Pull Type Locations <> 5033 Figure 147: Dye and Pull Type Locations
 
4932 Dye coverage of >50% (“D” and “E” in Figure 147) of any Type 2 or Type 3 BGA cracks are present in the test sample. <> 5035 Dye coverage of >50% (“D” and “E” in Figure 148) of any Type 2 or Type 3 BGA cracks are present in the test sample.
 
4934 Figure 147: Dye Coverage Percentage <> 5037 Figure 148: Dye Coverage Percentage
 
4961 Radiated and Conducted Emissions requirements are based on deployed geographical locations. Refer to Table 68 for details. <> 5064 Radiated and Conducted Emissions requirements are based on deployed geographical locations. Refer to Table 69 for details.
4962 Table 68: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location   5065 Table 69: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location
 
4987 Safety – requirements are listed in Table 69. <> 5090 Safety – requirements are listed in Table 70.
4988 Table 69: Safety Requirements   5091 Table 70: Safety Requirements
 
4997 The OCP NIC 3.0 card shall meet or exceed the following ESD immunity requirements listed in Table 70. <> 5100 The OCP NIC 3.0 card shall meet or exceed the following ESD immunity requirements listed in Table 71.
4998 Table 70: Immunity (ESD) Requirements   5101 Table 71: Immunity (ESD) Requirements
 
5164 - Section 3.4.1 – Clarify PWRBRK[0:1]# card pull up resistor value as 95kOhm or larger and must meet the TPWRBRK timing parameter per PCIe CEM. Provided recommended Baseboard value between 4.7 kOhm and 10 kOhm. <> 5267 - Section 3.4.1 – Clarify PWRBRK[0:1]# card pull up resistor value as 95kΩ or larger and must meet the TPWRBRK timing parameter per PCIe CEM. Provided recommended Baseboard value between 4.7 kΩ and 10 kΩ.
 
    -+ 5337 OCP NIC 3.0 Subgroup
      5338 - Section 1.2 – Acknowledgements section updated. Company name updates.
      5339 - Section 1.5 – Add Conventions section to define numerical representation in binary and hexadecimal radix. Standardized unit representations per the Bureau International des Poids et Mesures (BIPM). The number and unit are always separated with a space (example: for temperature “5 °C.” Units, where applicable, have been changed to their SI symbol. Most notably, “Ohm” is now represented with the uppercase letter omega “Ω”.
      5340 - Section 1.7.2.1, 1.7.2.2 – Minor update to clarify Primary connector is a 4C+ as defined in SFF-TA-1002 and consists of an “OCP Bay” and a “4C” region.
      5341 - Section 2.5.1, 2.5.2 – Update PCB break off note #3 to include feature max tolerances.
      5342 - Section 3.4.2 – Add recommendation on the PRSNTB{0:3] strapping resistors values as 0 Ω to 200 Ω.
      5343 - Section 3.4.5 – Scan Chain text clarification and diagram updates.
      5344 - Section 3.4.6 – Clarified the state of NIC_PWR_GOOD in relation to AUX_PWR_EN, MAIN_PWR_EN and the enabled power domain signals within operational tolerances in the truth table.
      5345 - Section 3.8 – Power state machine diagram updated - +12V_EDGE in ID Mode and Programming Mode marked as optional.
      5346 - Section 3.8.2, 3.8.5 – Clarifications to +12V_EDGE in ID/Programming mode. +12V_EDGE is now marked as optional in these two states. A max permissible leakage voltage is stated and the baseboard requires a bleed resistor.
      5347 - Section 3.9 – Clarification on the slot power envelope definition (assuming that is the same path the PCI SIG is going). Add 50W power class. Increased +12V_EDGE capacitance limits on 50W, 80W and 150W power class cards.
      5348 - Section 3.10.1 – Changed +12V_EDGE on normal power up sequence and programming mode power sequence diagrams to optional.
      5349 - Section 4.1 – Change PCIe VDM and MCTP Base over MCTP/PCIe VDM to N/A for RBT Type cards.
      5350 - Section 4.4 – Add Warning/Critical/Fatal temperature threshold example text as discussed in the June NIC 3.0 monthly meeting. Define Warning, Critical and Fatal criteria.
      5351 - Section 4.10.3 – Modify FRU OEM Record.
      5352 Offset 3 - Add new FRU record version for spec version 1.1.
      5353 Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables.
      5354 Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables.
      5355 Offset 21 – Add QSFP Power Class 8 (10.0 W transceivers).
      5356 Offset 24 – Add definition on which ports are supported in Aux Power Mode.
      5357 Offset 25 – Add definition for Hot aisle standby air flow requirements when using passive cables or RJ45.
      5358 Offset 27 – Add definition for Cold aisle standby air flow requirements when using passive cables or RJ45.
      5359 - Section 5.3.x – Add PCIe Gen5 text/fixture/test methodology updates. PCIe Gen5 for SFF uses a max -7.0 dB insertion loss at 16 GHz.
      5360 1.1.0
      5361 09/04/2020
 
5266 - Offset 9, 10 – Clarified hot aisle standby airflow requirement with an approach air temperature of 45°C. <> 5394 - Offset 9, 10 – Clarified hot aisle standby airflow requirement with an approach air temperature of 45 °C.
5267 - Offset 11, 12 – Clarified cold aisle standby airflow requirement with an approach air temperature of 35°C.   5395 - Offset 11, 12 – Clarified cold aisle standby airflow requirement with an approach air temperature of 35 °C.
 
    -+ 5413 9/xx/2020
      5414 - Offset 3 - Add new FRU record version for spec version 1.1.
      5415 - Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables.
      5416 - Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables.
      5417 - Offset 21 – Add QSFP Power Class 8 (10.0 W transceivers).
      5418 - Offset 24 – Add definition on which ports are supported in Aux Power Mode.
      5419 - Offset 25 – Add definition for Hot aisle standby air flow requirements when using passive cables or RJ45.
      5420 - Offset 27 – Add definition for Cold aisle standby air flow requirements when using passive cables or RJ45.
      5421 1.1.0