2 |
Version 1.0.9 |
<> |
2 |
Version 1.1.0 |
|
36 |
2.5.2 LFF Keep Out Zones 47 |
<> |
36 |
2.5.2 LFF Keep Out Zones 49 |
37 |
2.6 Baseboard Keep Out Zones 50 |
|
37 |
2.6 Baseboard Keep Out Zones 54 |
38 |
2.7 Insulation Requirements 51 |
|
38 |
2.7 Insulation Requirements 55 |
39 |
2.7.1 SFF Insulator 51 |
|
39 |
2.7.1 SFF Insulator 55 |
40 |
2.7.2 LFF Insulator 53 |
|
40 |
2.7.2 LFF Insulator 57 |
41 |
2.8 Critical-to-Function (CTF) Dimensions (SFF and LFF) 56 |
|
41 |
2.8 Critical-to-Function (CTF) Dimensions (SFF and LFF) 60 |
42 |
2.8.1 CTF Tolerances 56 |
|
42 |
2.8.1 CTF Tolerances 60 |
43 |
2.8.2 SFF Pull Tab CTF Dimensions 56 |
|
43 |
2.8.2 SFF Pull Tab CTF Dimensions 60 |
44 |
2.8.3 SFF Ejector Latch CTF Dimensions 58 |
|
44 |
2.8.3 SFF Ejector Latch CTF Dimensions 64 |
45 |
2.8.4 SFF Internal Lock CTF Dimensions 59 |
|
45 |
2.8.4 SFF Internal Lock CTF Dimensions 67 |
46 |
2.8.5 SFF Baseboard CTF Dimensions 60 |
|
46 |
2.8.5 SFF Baseboard CTF Dimensions 70 |
47 |
2.8.6 LFF Ejector Latch CTF Dimensions 63 |
|
47 |
2.8.6 LFF Ejector Latch CTF Dimensions 73 |
48 |
2.8.7 LFF Baseboard CTF Dimensions 64 |
|
48 |
2.8.7 LFF Baseboard CTF Dimensions 76 |
49 |
2.9 Labeling Requirements 67 |
|
49 |
2.9 Labeling Requirements 79 |
50 |
2.9.1 General Guidelines for Label Contents 67 |
|
50 |
2.9.1 General Guidelines for Label Contents 79 |
51 |
2.9.2 MAC Address Labeling Requirements 68 |
|
51 |
2.9.2 MAC Address Labeling Requirements 80 |
52 |
2.9.2.1 MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller 69 |
|
52 |
2.9.2.1 MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller 81 |
53 |
2.9.2.2 MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controllers 69 |
|
53 |
2.9.2.2 MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controllers 81 |
54 |
2.9.2.3 MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers 70 |
|
54 |
2.9.2.3 MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers 82 |
55 |
2.9.2.4 MAC Address Label Example 4 – Singe Port with Quad Host, Single Managed Controller 70 |
|
55 |
2.9.2.4 MAC Address Label Example 4 – Singe Port with Quad Host, Single Managed Controller 82 |
56 |
2.10 Mechanical CAD Package Examples 72 |
|
56 |
2.10 Mechanical CAD Package Examples 84 |
57 |
3 Electrical Interface Definition – Card Edge and Baseboard 73 |
|
57 |
3 Electrical Interface Definition – Card Edge and Baseboard 85 |
58 |
3.1 Card Edge Gold Finger Requirements 73 |
|
58 |
3.1 Card Edge Gold Finger Requirements 85 |
59 |
3.1.1 Gold Finger Mating Sequence 75 |
|
59 |
3.1.1 Gold Finger Mating Sequence 87 |
60 |
3.2 Baseboard Connector Requirements 79 |
|
60 |
3.2 Baseboard Connector Requirements 91 |
61 |
3.2.1 Right Angle Connector 79 |
|
61 |
3.2.1 Right Angle Connector 91 |
62 |
3.2.2 Right Angle Offset 80 |
|
62 |
3.2.2 Right Angle Offset 92 |
63 |
3.2.3 Straddle Mount Connector 80 |
|
63 |
3.2.3 Straddle Mount Connector 92 |
64 |
3.2.4 Straddle Mount Offset and PCB Thickness Options 82 |
|
64 |
3.2.4 Straddle Mount Offset and PCB Thickness Options 94 |
65 |
3.2.5 LFF Connector Locations 83 |
|
65 |
3.2.5 LFF Connector Locations 95 |
66 |
3.3 Pin Definition 83 |
|
66 |
3.3 Pin Definition 95 |
67 |
3.3.1 Primary Connector 84 |
|
67 |
3.3.1 Primary Connector 96 |
68 |
3.3.2 Secondary Connector 86 |
|
68 |
3.3.2 Secondary Connector 98 |
69 |
3.4 Signal Descriptions 87 |
|
69 |
3.4 Signal Descriptions 99 |
70 |
3.4.1 PCIe Interface Pins 87 |
|
70 |
3.4.1 PCIe Interface Pins 99 |
71 |
3.4.2 PCIe Present and Bifurcation Control Pins 93 |
|
71 |
3.4.2 PCIe Present and Bifurcation Control Pins 105 |
72 |
3.4.3 SMBus Interface Pins 96 |
|
72 |
3.4.3 SMBus Interface Pins 108 |
73 |
3.4.4 NC-SI over RBT Interface Pins 97 |
|
73 |
3.4.4 NC-SI over RBT Interface Pins 109 |
74 |
3.4.5 Scan Chain Pins 105 |
|
74 |
3.4.5 Scan Chain Pins 117 |
75 |
3.4.6 Power Supply Pins 113 |
|
75 |
3.4.6 Power Supply Pins 126 |
76 |
3.4.7 USB 2.0 (A68/A69) – Primary Connector Only 119 |
|
76 |
3.4.7 USB 2.0 (A68/A69) – Primary Connector Only 131 |
77 |
3.4.8 UART (A68/A69) – Secondary Connector Only 121 |
|
77 |
3.4.8 UART (A68/A69) – Secondary Connector Only 133 |
78 |
3.4.9 RFU[1:4] Pins 123 |
|
78 |
3.4.9 RFU[1:4] Pins 135 |
79 |
3.5 PCIe Bifurcation Mechanism 124 |
|
79 |
3.5 PCIe Bifurcation Mechanism 136 |
80 |
3.5.1 PCIe OCP NIC 3.0 Card to Baseboard Bifurcation Configuration (PRSNTA#, PRSNTB[3:0]#) 124 |
|
80 |
3.5.1 PCIe OCP NIC 3.0 Card to Baseboard Bifurcation Configuration (PRSNTA#, PRSNTB[3:0]#) 136 |
81 |
3.5.2 PCIe Baseboard to OCP NIC 3.0 Card Bifurcation Configuration (BIF[2:0]#) 124 |
|
81 |
3.5.2 PCIe Baseboard to OCP NIC 3.0 Card Bifurcation Configuration (BIF[2:0]#) 136 |
82 |
3.5.3 PCIe Bifurcation Decoder 125 |
|
82 |
3.5.3 PCIe Bifurcation Decoder 137 |
83 |
3.5.4 Bifurcation Detection Flow 127 |
|
83 |
3.5.4 Bifurcation Detection Flow 139 |
84 |
3.5.5 PCIe Bifurcation Examples 128 |
|
84 |
3.5.5 PCIe Bifurcation Examples 140 |
85 |
3.5.5.1 Single Host (1 x16) Baseboard with a 1 x16 OCP NIC 3.0 Card (Single Controller) 128 |
|
85 |
3.5.5.1 Single Host (1 x16) Baseboard with a 1 x16 OCP NIC 3.0 Card (Single Controller) 140 |
86 |
3.5.5.2 Single Host (2 x8) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controllers) 129 |
|
86 |
3.5.5.2 Single Host (2 x8) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controllers) 141 |
87 |
3.5.5.3 Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Single Controller) 130 |
|
87 |
3.5.5.3 Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Single Controller) 142 |
88 |
3.5.5.4 Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Quad Controllers) 131 |
|
88 |
3.5.5.4 Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Quad Controllers) 143 |
89 |
3.5.5.5 Single Host (1 x16, no Bifurcation) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controller) 132 |
|
89 |
3.5.5.5 Single Host (1 x16, no Bifurcation) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controller) 144 |
90 |
3.6 PCIe REFCLK and PERST# Mapping 133 |
|
90 |
3.6 PCIe REFCLK and PERST# Mapping 145 |
91 |
3.6.1 SFF PCIe REFCLK and PERST# Mapping 134 |
|
91 |
3.6.1 SFF PCIe REFCLK and PERST# Mapping 146 |
92 |
3.6.2 LFF PCIe REFCLK and PERST# Mapping 137 |
|
92 |
3.6.2 LFF PCIe REFCLK and PERST# Mapping 149 |
93 |
3.6.3 REFCLK and PERST# Mapping Expansion 139 |
|
93 |
3.6.3 REFCLK and PERST# Mapping Expansion 151 |
94 |
3.7 Port Numbering and LED Implementations 140 |
|
94 |
3.7 Port Numbering and LED Implementations 152 |
95 |
3.7.1 OCP NIC 3.0 Port Naming and Port Numbering 140 |
|
95 |
3.7.1 OCP NIC 3.0 Port Naming and Port Numbering 152 |
96 |
3.7.2 OCP NIC 3.0 Card LED Configuration 140 |
|
96 |
3.7.2 OCP NIC 3.0 Card LED Configuration 152 |
97 |
3.7.3 OCP NIC 3.0 Card LED Ordering 142 |
|
97 |
3.7.3 OCP NIC 3.0 Card LED Ordering 154 |
98 |
3.7.4 Baseboard LEDs Configuration over the Scan Chain 143 |
|
98 |
3.7.4 Baseboard LEDs Configuration over the Scan Chain 155 |
99 |
3.8 Power State Machine 145 |
|
99 |
3.8 Power State Machine 157 |
100 |
3.8.1 NIC Power Off 146 |
|
100 |
3.8.1 NIC Power Off 160 |
101 |
3.8.2 ID Mode 146 |
|
101 |
3.8.2 ID Mode 160 |
102 |
3.8.3 Aux Power Mode (S5) 146 |
|
102 |
3.8.3 Aux Power Mode 161 |
103 |
3.8.4 Main Power Mode (S0) 147 |
|
103 |
3.8.4 Main Power Mode 161 |
104 |
3.8.5 Programming Mode 147 |
|
104 |
3.8.5 Programming Mode 161 |
105 |
3.9 Power Supply Rail Requirements and Slot Power Envelopes 148 |
|
105 |
3.9 Power Supply Rail Requirements and Slot Power Envelopes 163 |
106 |
3.10 Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails 149 |
|
106 |
3.10 Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails 164 |
107 |
3.11 Power Sequence Timing Requirements 150 |
|
107 |
3.11 Power Sequence Timing Requirements 166 |
108 |
3.12 Digital I/O Specifications 154 |
|
108 |
3.12 Digital I/O Specifications 176 |
109 |
4 Management and Pre-OS Requirements 155 |
|
109 |
4 Management and Pre-OS Requirements 177 |
110 |
4.1 Sideband Management Interface and Transport 155 |
|
110 |
4.1 Sideband Management Interface and Transport 177 |
111 |
4.2 NC-SI Traffic 156 |
|
111 |
4.2 NC-SI Traffic 178 |
112 |
4.3 Management Controller (MC) MAC Address Provisioning 156 |
|
112 |
4.3 Management Controller (MC) MAC Address Provisioning 178 |
113 |
4.4 ASIC Die Temperature Reporting 158 |
|
113 |
4.4 ASIC Die Temperature Reporting 180 |
114 |
4.5 Power Consumption Reporting 161 |
|
114 |
4.5 Power Consumption Reporting 183 |
115 |
4.6 Pluggable Transceiver Module Status and Temperature Reporting 162 |
|
115 |
4.6 Pluggable Transceiver Module Status and Temperature Reporting 184 |
116 |
4.7 Management and Pre-OS Firmware Inventory and Update 162 |
|
116 |
4.7 Management and Pre-OS Firmware Inventory and Update 184 |
117 |
4.7.1 Secure Firmware 162 |
|
117 |
4.7.1 Secure Firmware 184 |
118 |
4.7.2 Firmware Inventory 163 |
|
118 |
4.7.2 Firmware Inventory 185 |
119 |
4.7.3 Firmware Inventory and Update in Multi-Host Environments 163 |
|
119 |
4.7.3 Firmware Inventory and Update in Multi-Host Environments 185 |
120 |
4.8 NC-SI Package Addressing and Hardware Arbitration Requirements 164 |
|
120 |
4.8 NC-SI Package Addressing and Hardware Arbitration Requirements 186 |
121 |
4.8.1 NC-SI over RBT Package Addressing 164 |
|
121 |
4.8.1 NC-SI over RBT Package Addressing 186 |
122 |
4.8.2 Arbitration Ring Connections 164 |
|
122 |
4.8.2 Arbitration Ring Connections 186 |
123 |
4.9 SMBus 2.0 Addressing Requirements 164 |
|
123 |
4.9 SMBus 2.0 Addressing Requirements 186 |
124 |
4.9.1 SMBus Address Map 165 |
|
124 |
4.9.1 SMBus Address Map 187 |
125 |
4.10 FRU EEPROM 165 |
|
125 |
4.10 FRU EEPROM 187 |
126 |
4.10.1 FRU EEPROM Addressing and Size 165 |
|
126 |
4.10.1 FRU EEPROM Addressing and Size 187 |
127 |
4.10.2 FRU EEPROM Write Protection 167 |
|
127 |
4.10.2 FRU EEPROM Write Protection 189 |
128 |
4.10.3 FRU EEPROM Content Requirements 167 |
|
128 |
4.10.3 FRU EEPROM Content Requirements 189 |
129 |
4.10.4 FRU Template 174 |
|
129 |
4.10.4 FRU Template 196 |
130 |
5 Routing Guidelines and Signal Integrity Considerations 174 |
|
130 |
5 Routing Guidelines and Signal Integrity Considerations 197 |
131 |
5.1 NC-SI over RBT 174 |
|
131 |
5.1 NC-SI over RBT 197 |
132 |
5.1.1 SFF Baseboard Requirements 176 |
|
132 |
5.1.1 SFF Baseboard Requirements 198 |
133 |
5.1.2 LFF Baseboard Requirements 176 |
|
133 |
5.1.2 LFF Baseboard Requirements 199 |
134 |
5.1.3 SFF OCP NIC 3.0 Card Requirements 177 |
|
134 |
5.1.3 SFF OCP NIC 3.0 Card Requirements 199 |
135 |
5.1.4 LFF OCP NIC 3.0 Card Requirements 178 |
|
135 |
5.1.4 LFF OCP NIC 3.0 Card Requirements 200 |
136 |
5.2 SMBus 2.0 178 |
|
136 |
5.2 SMBus 2.0 200 |
137 |
5.3 PCIe 179 |
|
137 |
5.3 PCIe 201 |
138 |
5.3.1 Channel Requirements 179 |
|
138 |
5.3.1 Channel Requirements 201 |
139 |
5.3.1.1 REFCLK requirements 179 |
|
139 |
5.3.1.1 REFCLK requirements 201 |
140 |
5.3.1.2 Add-in Card Electrical Budgets 179 |
|
140 |
5.3.1.2 Add-in Card Electrical Budgets 201 |
141 |
5.3.1.3 Baseboard Channel Budget 180 |
|
141 |
5.3.1.3 Baseboard Channel Budget 202 |
142 |
5.3.1.4 SFF-TA-1002 Connector Channel Budget 180 |
|
142 |
5.3.1.4 SFF-TA-1002 Connector Channel Budget 202 |
143 |
5.3.1.5 Differential Impedance (Informative) 180 |
|
143 |
5.3.1.5 Differential Impedance (Informative) 202 |
144 |
5.3.2 Test Fixtures 180 |
|
144 |
5.3.2 Test Fixtures 202 |
145 |
5.3.2.1 Compliance Load Board (CLB) 180 |
|
145 |
5.3.2.1 Compliance Load Board (CLB) 203 |
146 |
5.3.2.2 Compliance Baseboard (CBB) 182 |
|
146 |
5.3.2.2 Compliance Baseboard (CBB) 204 |
147 |
5.3.3 Test Methodology 182 |
|
147 |
5.3.3 Test Methodology 204 |
148 |
5.3.3.1 Test Setup 182 |
|
148 |
5.3.3.1 Test Setup 204 |
149 |
6 Thermal and Environmental 184 |
|
149 |
6 Thermal and Environmental 206 |
150 |
6.1 Airflow Direction 184 |
|
150 |
6.1 Airflow Direction 206 |
151 |
6.1.1 Hot Aisle Cooling 184 |
|
151 |
6.1.1 Hot Aisle Cooling 206 |
152 |
6.1.2 Cold Aisle Cooling 185 |
|
152 |
6.1.2 Cold Aisle Cooling 207 |
153 |
6.2 Thermal Design Guidelines 186 |
|
153 |
6.2 Thermal Design Guidelines 208 |
154 |
6.2.1 SFF Card ASIC Cooling – Hot Aisle 186 |
|
154 |
6.2.1 SFF Card ASIC Cooling – Hot Aisle 208 |
155 |
6.2.2 LFF Card ASIC Cooling – Hot Aisle 190 |
|
155 |
6.2.2 LFF Card ASIC Cooling – Hot Aisle 212 |
156 |
6.2.3 SFF Card ASIC Cooling – Cold Aisle 192 |
|
156 |
6.2.3 SFF Card ASIC Cooling – Cold Aisle 214 |
157 |
6.2.4 LFF Card ASIC Cooling – Cold Aisle 195 |
|
157 |
6.2.4 LFF Card ASIC Cooling – Cold Aisle 217 |
158 |
6.3 Thermal Simulation (CFD) Modeling 197 |
|
158 |
6.3 Thermal Simulation (CFD) Modeling 219 |
159 |
6.4 Thermal Test Fixture 197 |
|
159 |
6.4 Thermal Test Fixture 219 |
160 |
6.4.1 Test Fixture for SFF Card 198 |
|
160 |
6.4.1 Test Fixture for SFF Card 220 |
161 |
6.4.2 Test Fixture for LFF Card 200 |
|
161 |
6.4.2 Test Fixture for LFF Card 222 |
162 |
6.4.3 Test Fixture Airflow Direction 202 |
|
162 |
6.4.3 Test Fixture Airflow Direction 224 |
163 |
6.4.4 Thermal Test Fixture Candlestick Sensors 202 |
|
163 |
6.4.4 Thermal Test Fixture Candlestick Sensors 224 |
164 |
6.5 Card Sensor Requirements 204 |
|
164 |
6.5 Card Sensor Requirements 227 |
165 |
6.6 Card Cooling Tiers 204 |
|
165 |
6.6 Card Cooling Tiers 227 |
166 |
6.7 Non-Operational Shock & Vibration Testing 206 |
|
166 |
6.7 Non-Operational Shock & Vibration Testing 229 |
167 |
6.7.1 Shock & Vibe Test Fixture 206 |
|
167 |
6.7.1 Shock & Vibe Test Fixture 229 |
168 |
6.7.2 Test Procedure 207 |
|
168 |
6.7.2 Test Procedure 230 |
169 |
6.8 Dye and Pull Test Method 209 |
|
169 |
6.8 Dye and Pull Test Method 232 |
170 |
6.9 Gold Finger Plating Requirements 211 |
|
170 |
6.9 Gold Finger Plating Requirements 234 |
171 |
6.9.1 Host Side Gold Finger Plating Requirements 211 |
|
171 |
6.9.1 Host Side Gold Finger Plating Requirements 234 |
172 |
6.9.2 Line Side Gold Finger Durability Requirements 211 |
|
172 |
6.9.2 Line Side Gold Finger Durability Requirements 234 |
173 |
7 Regulatory 212 |
|
173 |
7 Regulatory 235 |
174 |
7.1 Required Compliance 212 |
|
174 |
7.1 Required Compliance 235 |
175 |
7.1.1 Required Environmental Compliance 212 |
|
175 |
7.1.1 Required Environmental Compliance 235 |
176 |
7.1.2 Required EMC Compliance 212 |
|
176 |
7.1.2 Required EMC Compliance 235 |
177 |
7.1.3 Required Product Safety Compliance 213 |
|
177 |
7.1.3 Required Product Safety Compliance 236 |
178 |
7.1.4 Required Immunity (ESD) Compliance 213 |
|
178 |
7.1.4 Required Immunity (ESD) Compliance 236 |
179 |
7.2 Recommended Compliance 214 |
|
179 |
7.2 Recommended Compliance 237 |
180 |
7.2.1 Recommended Environmental Compliance 214 |
|
180 |
7.2.1 Recommended Environmental Compliance 237 |
181 |
7.2.2 Recommended EMC Compliance 214 |
|
181 |
7.2.2 Recommended EMC Compliance 237 |
182 |
8 Revision History 215 |
|
182 |
8 Revision History 238 |
183 |
8.1 Document Revision History 215 |
|
183 |
8.1 Document Revision History 238 |
184 |
8.2 FRU Content Revision History 222 |
|
184 |
8.2 FRU Content Revision History 246 |
|
210 |
Figure 25: SFF Keep Out Zone – Top View – Detail A 45 |
<> |
210 |
Figure 25: SFF Keep Out Zone – Top View – Detail A 47 |
211 |
Figure 26: SFF Keep Out Zone – Bottom View 45 |
|
211 |
Figure 26: SFF Keep Out Zone – Bottom View 47 |
212 |
Figure 27: SFF Keep Out Zone – Side View 46 |
|
212 |
Figure 27: SFF Keep Out Zone – Side View 48 |
213 |
Figure 28: SFF Keep Out Zone – Side View – Detail D 46 |
|
213 |
Figure 28: SFF Keep Out Zone – Side View – Detail D 48 |
214 |
Figure 29: LFF Keep Out Zone – Top View 47 |
|
214 |
Figure 29: LFF Keep Out Zone – Top View 49 |
215 |
Figure 30: LFF Keep Out Zone – Top View – Detail A 48 |
|
215 |
Figure 30: LFF Keep Out Zone – Top View – Detail A 52 |
216 |
Figure 31: LFF Keep Out Zone – Bottom View 49 |
|
216 |
Figure 31: LFF Keep Out Zone – Bottom View 53 |
217 |
Figure 32: LFF Keep Out Zone – Side View 49 |
|
217 |
Figure 32: LFF Keep Out Zone – Side View 53 |
218 |
Figure 33: LFF Keep Out Zone – Side View – Detail D 50 |
|
218 |
Figure 33: LFF Keep Out Zone – Side View – Detail D 54 |
219 |
Figure 34: SFF Bottom Side Insulator (3D View) 51 |
|
219 |
Figure 34: SFF Bottom Side Insulator (3D View) 55 |
220 |
Figure 35: SFF Bottom Side Insulator (Top and Side View) 52 |
|
220 |
Figure 35: SFF Bottom Side Insulator (Top and Side View) 56 |
221 |
Figure 36: SFF Bottom Side Insulator (alternate) (Top and Side View) 53 |
|
221 |
Figure 36: SFF Bottom Side Insulator (alternate) (Top and Side View) 57 |
222 |
Figure 37: LFF Bottom Side Insulator (3D View) 53 |
|
222 |
Figure 37: LFF Bottom Side Insulator (3D View) 57 |
223 |
Figure 38: LFF Bottom Side Insulator (Top and Side View) 54 |
|
223 |
Figure 38: LFF Bottom Side Insulator (Top and Side View) 58 |
224 |
Figure 39: LFF Bottom Side Insulator (alternate) (Top and Side View) 55 |
|
224 |
Figure 39: LFF Bottom Side Insulator (alternate) (Top and Side View) 59 |
225 |
Figure 40: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View) 56 |
|
225 |
Figure 40: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View) 60 |
226 |
Figure 41: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View) 57 |
|
226 |
Figure 41: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View) 62 |
227 |
Figure 42: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View) 57 |
|
227 |
Figure 42: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View) 62 |
228 |
Figure 43: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View) 58 |
|
228 |
Figure 43: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View) 64 |
229 |
Figure 44: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View) 58 |
|
229 |
Figure 44: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View) 66 |
230 |
Figure 45: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View) 59 |
|
230 |
Figure 45: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View) 67 |
231 |
Figure 46: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View) 59 |
|
231 |
Figure 46: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View) 67 |
232 |
Figure 47: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Front View) 60 |
|
232 |
Figure 47: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Front View) 70 |
233 |
Figure 48: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Side View) 60 |
|
233 |
Figure 48: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Side View) 70 |
234 |
Figure 49: SFF Baseboard Chassis CTF Dimensions (Rear View) 60 |
|
234 |
Figure 49: SFF Baseboard Chassis CTF Dimensions (Rear View) 70 |
235 |
Figure 50: SFF Baseboard Chassis to Card Thumb Screw CTF Dimensions (Side View) 61 |
|
235 |
Figure 50: SFF Baseboard Chassis to Card Thumb Screw CTF Dimensions (Side View) 71 |
236 |
Figure 51: SFF Baseboard Chassis to Ejector lever Card CTF Dimensions (Side View) 61 |
|
236 |
Figure 51: SFF Baseboard Chassis to Ejector lever Card CTF Dimensions (Side View) 71 |
237 |
Figure 52: SFF Baseboard Chassis CTF Dimensions (Rear Rail Guide View) 61 |
|
237 |
Figure 52: SFF Baseboard Chassis CTF Dimensions (Rear Rail Guide View) 71 |
238 |
Figure 53: SFF Baseboard Chassis CTF Dimensions (Rail Guide Detail) – Detail C 62 |
|
238 |
Figure 53: SFF Baseboard Chassis CTF Dimensions (Rail Guide Detail) – Detail C 72 |
239 |
Figure 54: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View) 63 |
|
239 |
Figure 54: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View) 73 |
240 |
Figure 55: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View) 63 |
|
240 |
Figure 55: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View) 75 |
241 |
Figure 56: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View) 64 |
|
241 |
Figure 56: LFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View) 76 |
242 |
Figure 57: LFF Baseboard Chassis CTF Dimensions (Rear View) 64 |
|
242 |
Figure 57: LFF Baseboard Chassis CTF Dimensions (Rear View) 76 |
243 |
Figure 58: LFF Baseboard Chassis CTF Dimensions (Side View) 65 |
|
243 |
Figure 58: LFF Baseboard Chassis CTF Dimensions (Side View) 77 |
244 |
Figure 59: LFF Baseboard Chassis CTF Dimensions (Rail Guide View) 65 |
|
244 |
Figure 59: LFF Baseboard Chassis CTF Dimensions (Rail Guide View) 77 |
245 |
Figure 60: LFF Baseboard Chassis CTF Dimensions (Rail Guide – Detail C) 65 |
|
245 |
Figure 60: LFF Baseboard Chassis CTF Dimensions (Rail Guide – Detail C) 77 |
246 |
Figure 61: SFF Label Area Example 67 |
|
246 |
Figure 61: SFF Label Area Example 79 |
247 |
Figure 62: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller 69 |
|
247 |
Figure 62: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller 81 |
248 |
Figure 63: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller 70 |
|
248 |
Figure 63: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller 82 |
249 |
Figure 64: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers 70 |
|
249 |
Figure 64: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers 82 |
250 |
Figure 65: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller 71 |
|
250 |
Figure 65: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller 83 |
251 |
Figure 66: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller 71 |
|
251 |
Figure 66: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller 83 |
252 |
Figure 67: SFF Primary Connector Gold Finger Dimensions – x16 – Top Side (“B” Pins) 73 |
|
252 |
Figure 67: SFF Primary Connector Gold Finger Dimensions – x16 – Top Side (“B” Pins) 85 |
253 |
Figure 68: SFF Primary Connector Card Profile Dimensions 74 |
|
253 |
Figure 68: SFF Primary Connector Card Profile Dimensions 86 |
254 |
Figure 69: SFF Primary Conector Gold Finger - Detail D 74 |
|
254 |
Figure 69: SFF Primary Conector Gold Finger - Detail D 86 |
255 |
Figure 70: LFF Gold Finger Dimensions – x32 – Top Side (“B” Pins) 75 |
|
255 |
Figure 70: LFF Gold Finger Dimensions – x32 – Top Side (“B” Pins) 87 |
256 |
Figure 71: LFF Gold Finger Dimensions – x32 – Bottom Side (“A” Pins) 75 |
|
256 |
Figure 71: LFF Gold Finger Dimensions – x32 – Bottom Side (“A” Pins) 87 |
257 |
Figure 72: 168-pin Base Board Primary Connector – Right Angle 79 |
|
257 |
Figure 72: 168-pin Base Board Primary Connector – Right Angle 91 |
258 |
Figure 73: 140-pin Base Board Secondary Connector – Right Angle 80 |
|
258 |
Figure 73: 140-pin Base Board Secondary Connector – Right Angle 92 |
259 |
Figure 74: OCP NIC 3.0 Card and Host Offset for Right Angle Connectors 80 |
|
259 |
Figure 74: OCP NIC 3.0 Card and Host Offset for Right Angle Connectors 92 |
260 |
Figure 75: 168-pin Base Board Primary Connector – Straddle Mount 81 |
|
260 |
Figure 75: 168-pin Base Board Primary Connector – Straddle Mount 93 |
261 |
Figure 76: 140-pin Base Board Secondary Connector – Straddle Mount 81 |
|
261 |
Figure 76: 140-pin Base Board Secondary Connector – Straddle Mount 93 |
262 |
Figure 77: OCP NIC 3.0 Card and Baseboard PCB Thickness Options for Straddle Mount Connectors 82 |
|
262 |
Figure 77: OCP NIC 3.0 Card and Baseboard PCB Thickness Options for Straddle Mount Connectors 94 |
263 |
Figure 78: 0 mm Offset (Coplanar) for 0.062” Thick Baseboards 82 |
|
263 |
Figure 78: 0 mm Offset (Coplanar) for 0.062” Thick Baseboards 94 |
264 |
Figure 79: 0.3 mm Offset for 0.076” Thick Baseboards 83 |
|
264 |
Figure 79: 0.3 mm Offset for 0.076” Thick Baseboards 95 |
265 |
Figure 80: Primary and Secondary Connector Locations for LFF Support with Right Angle Connectors 83 |
|
265 |
Figure 80: Primary and Secondary Connector Locations for LFF Support with Right Angle Connectors 95 |
266 |
Figure 81: Primary and Secondary Connector Locations for LFF Support with Straddle Mount Connectors 83 |
|
266 |
Figure 81: Primary and Secondary Connector Locations for LFF Support with Straddle Mount Connectors 95 |
267 |
Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[2:0]#) 95 |
|
267 |
Figure 82: PCIe Present and Bifurcation Control Pins (Baseboard Controlled BIF[2:0]#) 107 |
268 |
Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[2:0]#) 95 |
|
268 |
Figure 83: PCIe Present and Bifurcation Control Pins (Static BIF[2:0]#) 107 |
269 |
Figure 84: Example SMBus Connections 97 |
|
269 |
Figure 84: Example SMBus Connections 109 |
270 |
Figure 85: NC-SI over RBT Connection Example – Single Primary Connector 103 |
|
270 |
Figure 85: NC-SI over RBT Connection Example – Single Primary Connector 115 |
271 |
Figure 86: NC-SI over RBT Connection Example – Dual Primary Connectors 104 |
|
271 |
Figure 86: NC-SI over RBT Connection Example – Dual Primary Connectors 116 |
272 |
Figure 87: Scan Chain Timing Diagram Example 1 107 |
|
272 |
Figure 87: Scan Chain Timing Diagram Example 1 119 |
273 |
Figure 88: Scan Chain Timing Diagram Example 2 107 |
|
273 |
Figure 88: Scan Chain Timing Diagram Example 2 119 |
274 |
Figure 89: Scan Chain Connection Example 113 |
|
274 |
Figure 89: Scan Chain Connection Example 125 |
275 |
Figure 90: Example Power Supply Topology 118 |
|
275 |
Figure 90: Example Power Supply Topology 130 |
276 |
Figure 91: USB 2.0 Connection Example – Basic Connectivity 120 |
|
276 |
Figure 91: USB 2.0 Connection Example – Basic Connectivity 132 |
277 |
Figure 92: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity 120 |
|
277 |
Figure 92: USB 2.0 Connection Example – USB-Serial / USB-JTAG Connectivity 132 |
278 |
Figure 93: UART Connection Example 122 |
|
278 |
Figure 93: UART Connection Example 134 |
279 |
Figure 94: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller) 128 |
|
279 |
Figure 94: Single Host (1 x16) and 1 x16 OCP NIC 3.0 Card (Single Controller) 140 |
280 |
Figure 95: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers) 129 |
|
280 |
Figure 95: Single Host (2 x8) and 2 x8 OCP NIC 3.0 Card (Dual Controllers) 141 |
281 |
Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller) 130 |
|
281 |
Figure 96: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Single Controller) 142 |
282 |
Figure 97: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers) 131 |
|
282 |
Figure 97: Quad Hosts (4 x4) and 4 x4 OCP NIC 3.0 Card (Quad Controllers) 143 |
283 |
Figure 98: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers) 132 |
|
283 |
Figure 98: Single Host with no Bifurcation (1 x16) and 2 x8 OCP NIC 3.0 Card (Dual Controllers) 144 |
284 |
Figure 99: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links 134 |
|
284 |
Figure 99: SFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links 146 |
285 |
Figure 100: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links 135 |
|
285 |
Figure 100: SFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links 147 |
286 |
Figure 101: SFF PCIe REFCLK Mapping – Quad Host – 4 Links 136 |
|
286 |
Figure 101: SFF PCIe REFCLK Mapping – Quad Host – 4 Links 148 |
287 |
Figure 102: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links 137 |
|
287 |
Figure 102: LFF PCIe REFCLK Mapping – Single Host – 1, 2 and 4 links 149 |
288 |
Figure 103: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links 138 |
|
288 |
Figure 103: LFF PCIe REFCLK Mapping – Dual Host – 2 and 4 links 150 |
289 |
Figure 104: LFF PCIe REFCLK Mapping – Quad Host – 4 Links 139 |
|
289 |
Figure 104: LFF PCIe REFCLK Mapping – Quad Host – 4 Links 151 |
290 |
Figure 105: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement 143 |
|
290 |
Figure 105: Port and LED Ordering – Example SFF Link/Activity and Speed LED Placement 155 |
291 |
Figure 106: Baseboard Power States 145 |
|
291 |
Figure 106: Baseboard Power States 157 |
292 |
Figure 107: Power-Up Sequencing – Normal Operation 150 |
|
292 |
Figure 107: Power-Up Sequencing – Normal Operation 166 |
293 |
Figure 108: Power-Down Sequencing – Normal Operation 151 |
|
293 |
Figure 108: Power-Down Sequencing – Normal Operation 169 |
294 |
Figure 109: Programming Mode Sequencing 152 |
|
294 |
Figure 109: Programming Mode Sequencing 172 |
295 |
Figure 110: FRU EEPROM Writes with Double Byte Addressing 166 |
|
295 |
Figure 110: FRU EEPROM Writes with Double Byte Addressing 188 |
296 |
Figure 111: FRU EEPROM Reads with Double Byte Addressing 166 |
|
296 |
Figure 111: FRU EEPROM Reads with Double Byte Addressing 188 |
297 |
Figure 112: FRU Update Flow 167 |
|
297 |
Figure 112: FRU Update Flow 189 |
298 |
Figure 113: NC-SI over RBT Timing Budget Topology 175 |
|
298 |
Figure 113: NC-SI over RBT Timing Budget Topology 198 |
299 |
Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer 178 |
|
299 |
Figure 114: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – No Clock Buffer 200 |
300 |
Figure 115: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer 178 |
|
300 |
Figure 115: NC-SI over RBT Propagation Delay Matching for Two Target ASICs – Clock Buffer 200 |
301 |
Figure 116: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF 180 |
|
301 |
Figure 116: PCIe Load Board Test Fixture for OCP NIC 3.0 SFF 203 |
302 |
Figure 117: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF 182 |
|
302 |
Figure 117: PCIe Base Board Test Fixture for OCP NIC 3.0 SFF 204 |
303 |
Figure 118: Airflow Direction for Hot Aisle Cooling (SFF and LFF) 184 |
|
303 |
Figure 118: Airflow Direction for Hot Aisle Cooling (SFF and LFF) 206 |
304 |
Figure 119: Airflow Direction for Cold Aisle Cooling (SFF and LFF) 185 |
|
304 |
Figure 119: Airflow Direction for Cold Aisle Cooling (SFF and LFF) 207 |
305 |
Figure 120: ASIC Supportable Power for Hot Aisle Cooling – SFF 186 |
|
305 |
Figure 120: ASIC Supportable Power for Hot Aisle Cooling – SFF 208 |
306 |
Figure 121: OCP NIC 3.0 SFF Reference Design and CFD Geometry 187 |
|
306 |
Figure 121: OCP NIC 3.0 SFF Reference Design and CFD Geometry 209 |
307 |
Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling 188 |
|
307 |
Figure 122: Server System Airflow Capability – SFF Card Hot Aisle Cooling 210 |
308 |
Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode 189 |
|
308 |
Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in Aux Power Mode 211 |
309 |
Figure 124: ASIC Supportable Power for Hot Aisle Cooling – LFF Card 190 |
|
309 |
Figure 124: ASIC Supportable Power for Hot Aisle Cooling – LFF Card 212 |
310 |
Figure 125: OCP NIC 3.0 LFF Reference Design and CFD Geometry 190 |
|
310 |
Figure 125: OCP NIC 3.0 LFF Reference Design and CFD Geometry 212 |
311 |
Figure 126: Server System Airflow Capability – LFF Card Hot Aisle Cooling 192 |
|
311 |
Figure 126: Server System Airflow Capability – LFF Card Hot Aisle Cooling 214 |
312 |
Figure 127: ASIC Supportable Power for Cold Aisle Cooling – SFF Card 193 |
|
312 |
Figure 127: ASIC Supportable Power for Cold Aisle Cooling – SFF Card 215 |
313 |
Figure 128: Server System Airflow Capability – SFF Cold Aisle Cooling 194 |
|
313 |
Figure 128: Server System Airflow Capability – SFF Cold Aisle Cooling 216 |
314 |
Figure 129: ASIC Supportable Power Comparison – SFF Card 194 |
|
314 |
Figure 129: ASIC Supportable Power Comparison – SFF Card 216 |
315 |
Figure 130: ASIC Supportable Power for Cold Aisle Cooling – LFF Card 195 |
|
315 |
Figure 130: ASIC Supportable Power for Cold Aisle Cooling – LFF Card 217 |
316 |
Figure 131: Server System Airflow Capability – LFF Cold Aisle Cooling 196 |
|
316 |
Figure 131: Server System Airflow Capability – LFF Cold Aisle Cooling 218 |
317 |
Figure 132: ASIC Supportable Power Comparison – LFF Card 196 |
|
317 |
Figure 132: ASIC Supportable Power Comparison – LFF Card 218 |
318 |
Figure 133: SFF Thermal Test Fixture Preliminary Design 198 |
|
318 |
Figure 133: SFF Thermal Test Fixture Preliminary Design 220 |
319 |
Figure 134: SFF Thermal Test Fixture Preliminary Design – Cover Removed 199 |
|
319 |
Figure 134: SFF Thermal Test Fixture Preliminary Design – Cover Removed 221 |
320 |
Figure 135: SFF Card Thermal Test Fixture PCB 199 |
|
320 |
Figure 135: SFF Card Thermal Test Fixture PCB 221 |
321 |
Figure 136: LFF Card Thermal Test Fixture Design 200 |
|
321 |
Figure 136: LFF Card Thermal Test Fixture Design 222 |
322 |
Figure 137: LFF Card Thermal Test Fixture Design – Cover Removed 200 |
|
322 |
Figure 137: LFF Card Thermal Test Fixture Design – Cover Removed 222 |
323 |
Figure 138: LFF Card Thermal Test Fixture PCB 201 |
|
323 |
Figure 138: LFF Card Thermal Test Fixture PCB 223 |
324 |
Figure 139: Thermal Test Fixture Airflow Direction 202 |
|
324 |
Figure 139: Thermal Test Fixture Airflow Direction 224 |
|
|
|
325 |
Figure 140: External Thermocouple Placement for Cold Aisle Inlet Temperature Measurement 225 |
325 |
Figure 140: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 203 |
|
326 |
Figure 140: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 226 |
326 |
Figure 141: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 203 |
|
327 |
Figure 141: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow 226 |
327 |
Figure 142: Graphical View of Card Cooling Tiers 205 |
|
328 |
Figure 142: Graphical View of Card Cooling Tiers 228 |
328 |
Figure 143: Typical Operating Range for Hot Aisle Configurations 205 |
|
329 |
Figure 143: Typical Operating Range for Hot Aisle Configurations 228 |
329 |
Figure 144: Typical Operating Range for Cold Aisle Configurations 206 |
|
330 |
Figure 144: Typical Operating Range for Cold Aisle Configurations 229 |
330 |
Figure 145: SFF Shock and Vibe Fixture 207 |
|
331 |
Figure 145: SFF Shock and Vibe Fixture 230 |
331 |
Figure 146: LFF Shock and Vibe Fixture 207 |
|
332 |
Figure 146: LFF Shock and Vibe Fixture 230 |
332 |
Figure 147: Dye and Pull Type Locations 210 |
|
333 |
Figure 147: Dye and Pull Type Locations 233 |
333 |
Figure 148: Dye Coverage Percentage 210 |
|
334 |
Figure 148: Dye Coverage Percentage 233 |
|
344 |
Table 10: CTF Default Tolerances (SFF and LFF OCP NIC 3.0) 56 |
<> |
345 |
Table 10: CTF Default Tolerances (SFF and LFF OCP NIC 3.0) 60 |
345 |
Table 11: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller 69 |
|
346 |
Table 11: MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller 81 |
346 |
Table 12: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller 69 |
|
347 |
Table 12: MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controller 81 |
347 |
Table 13: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controller 70 |
|
348 |
Table 13: MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controller 82 |
348 |
Table 14: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller 71 |
|
349 |
Table 14: MAC Address Label Example 4 – Single Port with Quad Host, Single Managed Controller 83 |
349 |
Table 15: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller 71 |
|
350 |
Table 15: MAC Address Label Example 5 – Octal Port with Single Host, Octal Managed Controller 83 |
350 |
Table 16: NIC Implementation Examples and 3D CAD 72 |
|
351 |
Table 16: NIC Implementation Examples and 3D CAD 84 |
351 |
Table 17: Contact Mating Positions for the Primary Connector 75 |
|
352 |
Table 17: Contact Mating Positions for the Primary Connector 87 |
352 |
Table 18: Contact Mating Positions for the Secondary Connector 77 |
|
353 |
Table 18: Contact Mating Positions for the Secondary Connector 89 |
353 |
Table 19: Right Angle Connector Options 79 |
|
354 |
Table 19: Right Angle Connector Options 91 |
354 |
Table 20: Straddle Mount Connector Options 80 |
|
355 |
Table 20: Straddle Mount Connector Options 92 |
355 |
Table 21: Primary Connector Pin Definition (x16) (4C+) 84 |
|
356 |
Table 21: Primary Connector Pin Definition (x16) (4C+) 96 |
356 |
Table 22: Secondary Connector Pin Definition (x16) (4C) 86 |
|
357 |
Table 22: Secondary Connector Pin Definition (x16) (4C) 98 |
357 |
Table 23: Pin Descriptions – PCIe 87 |
|
358 |
Table 23: Pin Descriptions – PCIe 100 |
358 |
Table 24: Pin Descriptions – PCIe Present and Bifurcation Control Pins 93 |
|
359 |
Table 24: Pin Descriptions – PCIe Present and Bifurcation Control Pins 105 |
359 |
Table 25: Pin Descriptions – SMBus 96 |
|
360 |
Table 25: Pin Descriptions – SMBus 108 |
360 |
Table 26: Pin Descriptions – NC-SI over RBT 97 |
|
361 |
Table 26: Pin Descriptions – NC-SI over RBT 109 |
361 |
Table 27: Pin Descriptions – Scan Chain 105 |
|
362 |
Table 27: Pin Descriptions – Scan Chain 117 |
362 |
Table 28: Scan Chain Timing Requirements – Baseboard Side 107 |
|
363 |
Table 28: Scan Chain Timing Requirements – Baseboard Side 119 |
363 |
Table 29: Scan Chain Timing Requirements – OCP NIC 3.0 Card Side 107 |
|
364 |
Table 29: Scan Chain Timing Requirements – OCP NIC 3.0 Card Side 119 |
364 |
Table 30: Pin Descriptions – Scan Chain DATA_OUT Bit Definition 108 |
|
365 |
Table 30: Pin Descriptions – Scan Chain DATA_OUT Bit Definition 120 |
365 |
Table 31: Pin Descriptions – Scan Chain DATA_IN Bit Definition 108 |
|
366 |
Table 31: Pin Descriptions – Scan Chain DATA_IN Bit Definition 121 |
366 |
Table 32: Pin Descriptions – Power 114 |
|
367 |
Table 32: Pin Descriptions – Power 126 |
367 |
Table 33: Pin Descriptions – USB 2.0 – Primary Connector only 119 |
|
368 |
Table 33: Pin Descriptions – USB 2.0 – Primary Connector only 131 |
368 |
Table 34: Pin Descriptions – UART – Secondary Connector Only 121 |
|
369 |
Table 34: Pin Descriptions – UART – Secondary Connector Only 133 |
369 |
Table 35: Pin Descriptions – RFU[1:4] 123 |
|
370 |
Table 35: Pin Descriptions – RFU[1:4] 135 |
370 |
Table 36: PCIe Bifurcation Decoder for x32, x16, x8, x4, x2 and x1 Card Widths 126 |
|
371 |
Table 36: PCIe Bifurcation Decoder for x32, x16, x8, x4, x2 and x1 Card Widths 138 |
371 |
Table 37: PCIe REFCLK and PERST Associations 133 |
|
372 |
Table 37: PCIe REFCLK and PERST Associations 145 |
372 |
Table 38: SFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links 133 |
|
373 |
Table 38: SFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2 and 4 Links 145 |
373 |
Table 39: LFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2, 4 and 8 Links 133 |
|
374 |
Table 39: LFF PCIe Link / REFCLKn / PERSTn mapping for 1, 2, 4 and 8 Links 145 |
374 |
Table 40: OCP NIC 3.0 Card LED Configuration with Two Physical LEDs per Port 141 |
|
375 |
Table 40: OCP NIC 3.0 Card LED Configuration with Two Physical LEDs per Port 153 |
375 |
Table 41: Available Card Functions per Power State 146 |
|
376 |
Table 41: Available Card Functions per Power State 160 |
376 |
Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes 148 |
|
377 |
Table 42: Baseboard Power Supply Rail Requirements – Slot Power Envelopes 163 |
377 |
Table 43: Power Sequencing Parameters 152 |
|
378 |
Table 43: Power Sequencing Parameters 174 |
378 |
Table 44: Digital I/O DC specifications 154 |
|
379 |
Table 44: Digital I/O DC specifications 176 |
379 |
Table 45: Digital I/O AC specifications 154 |
|
380 |
Table 45: Digital I/O AC specifications 176 |
380 |
Table 46: OCP NIC 3.0 Management Implementation Definitions 155 |
|
381 |
Table 46: OCP NIC 3.0 Management Implementation Definitions 177 |
381 |
Table 47: Sideband Management Interface and Transport Requirements 155 |
|
382 |
Table 47: Sideband Management Interface and Transport Requirements 177 |
382 |
Table 48: NC-SI Traffic Requirements 156 |
|
383 |
Table 48: NC-SI Traffic Requirements 178 |
383 |
Table 49: MC MAC Address Provisioning Requirements 156 |
|
384 |
Table 49: MC MAC Address Provisioning Requirements 178 |
384 |
Table 50: Threshold Severity Level vs Example Threshold Values 159 |
|
385 |
Table 50: Threshold Severity Level vs Example Threshold Values 181 |
385 |
Table 51: Temperature Reporting Requirements 159 |
|
386 |
Table 51: Temperature Reporting Requirements 181 |
386 |
Table 52: Power Consumption Reporting Requirements 161 |
|
387 |
Table 52: Power Consumption Reporting Requirements 183 |
387 |
Table 53: Pluggable Module Status Reporting Requirements 162 |
|
388 |
Table 53: Pluggable Module Status Reporting Requirements 184 |
388 |
Table 54: Management and Pre-OS Firmware Inventory and Update Requirements 162 |
|
389 |
Table 54: Management and Pre-OS Firmware Inventory and Update Requirements 184 |
389 |
Table 55: Slot_ID[1:0] to Package ID[2:0] Mapping 164 |
|
390 |
Table 55: Slot_ID[1:0] to Package ID[2:0] Mapping 186 |
390 |
Table 56: FRU EEPROM Address Map 165 |
|
391 |
Table 56: FRU EEPROM Address Map 187 |
391 |
Table 57: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00 168 |
|
392 |
Table 57: FRU EEPROM Record – OEM Record 0xC0, Offset 0x00 190 |
392 |
Table 58: NC-SI over RBT Timing Parameters 175 |
|
393 |
Table 58: NC-SI over RBT Timing Parameters 197 |
393 |
Table 59: PCIe Electrical Budgets 179 |
|
394 |
Table 59: PCIe Electrical Budgets 201 |
394 |
Table 60: PCIe Test Fixtures for OCP NIC 3.0 180 |
|
395 |
Table 60: PCIe Test Fixtures for OCP NIC 3.0 202 |
395 |
Table 61: Hot Aisle Air Temperature Boundary Conditions 185 |
|
396 |
Table 61: Hot Aisle Air Temperature Boundary Conditions 207 |
396 |
Table 62: Hot Aisle Airflow Boundary Conditions 185 |
|
397 |
Table 62: Hot Aisle Airflow Boundary Conditions 207 |
397 |
Table 63: Cold Aisle Air Temperature Boundary Conditions 185 |
|
398 |
Table 63: Cold Aisle Air Temperature Boundary Conditions 207 |
398 |
Table 64: Cold Aisle Airflow Boundary Conditions 186 |
|
399 |
Table 64: Cold Aisle Airflow Boundary Conditions 208 |
399 |
Table 65: Reference OCP NIC 3.0 SFF Card Geometry 187 |
|
400 |
Table 65: Reference OCP NIC 3.0 SFF Card Geometry 209 |
400 |
Table 66: Reference OCP NIC 3.0 LFF Card Geometry 191 |
|
401 |
Table 66: Reference OCP NIC 3.0 LFF Card Geometry 213 |
401 |
Table 67: Card Cooling Tier Definitions (LFM) 204 |
|
402 |
Table 67: Card Cooling Tier Definitions (LFM) 227 |
402 |
Table 68: Random Vibration Testing 1.88 GRMS Profile 208 |
|
403 |
Table 68: Random Vibration Testing 1.88 GRMS Profile 231 |
403 |
Table 69: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location 212 |
|
404 |
Table 69: FCC Class A Radiated and Conducted Emissions Requirements Based on Geographical Location 235 |
404 |
Table 70: Safety Requirements 213 |
|
405 |
Table 70: Safety Requirements 236 |
405 |
Table 71: Immunity (ESD) Requirements 213 |
|
406 |
Table 71: Immunity (ESD) Requirements 236 |
|
2728 |
Note: The OCP NIC 3.0 card shall implement protection methods to prevent leakage or low impedance paths between the VAUX and VMAIN power domains in the event that a powered-down NIC is physically present in a powered-up baseboard. This specification provides example isolation implementations in the signal description text and appropriate figures. OCP NIC 3.0 implementers may choose to do a different implementation as long as the isolation requirements are met and the same result is achieved. |
<> |
2729 |
Note 1: The OCP NIC 3.0 card shall implement protection methods to prevent leakage or low impedance paths between the VAUX and VMAIN power domains if a powered-down NIC is physically present in a powered-up baseboard. This specification provides example isolation implementations in the signal description text and appropriate figures. OCP NIC 3.0 implementers may choose to do a different implementation as long as the isolation requirements are met and the same result is achieved. |
|
|
|
2730 |
Note 2: The terms Aux Power Mode and Main Power Mode are used within this specification and define the corresponding ACPI power states of the system. |
|
|
|
2731 |
Aux Power Mode corresponds to the S5 ACPI power state and may also include ACPI power states S3 or S4 depending on the implementation. In Aux Power Mode, AUX_PWR_EN==1, and MAIN_PWR_EN==0. |
|
|
|
2732 |
Main Power Mode corresponds to the S0 ACPI power state on the system and may also correspond to ACPI power state S1 depending on the implementation. In Main Power Mode, AUX_PWR_EN==1, and MAIN_PWR_EN==1. |
|
2963 |
For OCP NIC 3.0 cards, this signal shall be connected between the endpoint silicon WAKE# pin(s) and the card edge through an isolation buffer. The WAKE# signal shall not assert until the PCIe card is in the D3 state according to the PCIe CEM specification to prevent false WAKE# events. For OCP NIC 3.0, the WAKE# pin shall be buffered or otherwise isolated from the host until the aux voltage source is present. Examples of this are shown in Section 3.5.5 by gating via an on-board “AUX_PWR_GOOD” signal to indicate all the NIC AUX power rails are stable. The PCIe CEM specification also shows an example in the WAKE# signal section. |
<> |
2967 |
For OCP NIC 3.0 cards, this signal shall be connected between the endpoint silicon WAKE# pin(s) and the card edge through an isolation buffer. The WAKE# signal shall not assert until the PCIe card is in the D3 state according to the PCIe CEM specification to prevent false WAKE# events. For OCP NIC 3.0, the WAKE# pin shall be buffered or otherwise isolated from the host until the aux voltage source is present. Examples of this are shown in Section 3.5.5 by gating via an on-board “AUX_PWR_GOOD” signal to indicate all the NIC Aux power rails are stable. The PCIe CEM specification also shows an example in the WAKE# signal section. |
|
3014 |
For OCP NIC 3.0 cards, these signals shall connect to the endpoint bifurcation pins if it is supported. The BIF[2:0]# signals shall be left as no connects if end point bifurcation is not supported. The value of the BIF[2:0]# pins are latched by the OCP NIC 3.0 card upon entering the AUX power mode state (when AUX_PWR_EN=1 and NIC_PWR_GOOD=1). |
<> |
3018 |
For OCP NIC 3.0 cards, these signals shall connect to the endpoint bifurcation pins if it is supported. The BIF[2:0]# signals shall be left as no connects if end point bifurcation is not supported. The value of the BIF[2:0]# pins are latched by the OCP NIC 3.0 card upon entering Aux Power Mode (when AUX_PWR_EN=1 and NIC_PWR_GOOD=1). |
|
3047 |
Note: The RBT pins must provide the ability to be isolated on the baseboard side when AUX_PWR_EN=0 or when (AUX_PWR_EN=1 and NIC_PWR_GOOD=0). The RBT pins shall remain isolated until the power state machine has transitioned to AUX power mode or to Main Power Mode along with a valid indication of NIC_PWR_GOOD. This prevents a leakage path through unpowered silicon. The RBT REF_CLK must also be disabled until AUX_PWR_EN=1 and NIC_PWR_GOOD=1. Example buffering implementations are shown in Figure 85 and Figure 86. The isolator shall be controlled on the baseboard with a signal called RBT_ISOLATE#. |
<> |
3051 |
Note: The RBT pins must provide the ability to be isolated on the baseboard side when AUX_PWR_EN=0 or when (AUX_PWR_EN=1 and NIC_PWR_GOOD=0). The RBT pins shall remain isolated until the power state machine has transitioned to Aux Power Mode or to Main Power Mode along with a valid indication of NIC_PWR_GOOD. This prevents a leakage path through unpowered silicon. The RBT REF_CLK must also be disabled until AUX_PWR_EN=1 and NIC_PWR_GOOD=1. Example buffering implementations are shown in Figure 85 and Figure 86. The isolator shall be controlled on the baseboard with a signal called RBT_ISOLATE#. |
|
3059 |
For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the Primary Connector OCP bay. The RBT_REF_CLK shall not be driven until the card has transitioned into AUX Power Mode. The RBT_REF_CLK shall be continuous once it has started. |
<> |
3063 |
For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the Primary Connector OCP bay. The RBT_REF_CLK shall not be driven until the card has transitioned into Aux Power Mode. The RBT_REF_CLK shall be continuous once it has started. |
|
3302 |
When high, FAN_ON_AUX shall request the system fan to be enabled for extra cooling in the S5 state. |
<> |
3306 |
When high, FAN_ON_AUX shall request the system fan to be enabled for extra cooling in Aux Power Mode. |
|
3305 |
0b0 – The system fan is not requested/off in S5. |
<> |
3309 |
0b0 – The system fan is not requested/off in Aux Power Mode. |
3306 |
0b1 – The system fan is requested/on in S5. |
|
3310 |
0b1 – The system fan is requested/on in Aux Power Mode. |
|
3461 |
The MAIN_PWR_EN pin is driven by the baseboard for normal operation in the S0 or S1 power state and may only be asserted when AUX_PWR_EN is already asserted. The MAIN_PWR_EN pin must be implemented on baseboard systems, but may optionally be used to control main power rail power supplies by the OCP NIC 3.0 card depending on the end point silicon implementation. Depending on the silicon vendor, end point devices may be able to operate in a single power domain, or may require separate power domains to function. |
<> |
3465 |
The MAIN_PWR_EN pin is driven by the baseboard for normal operation and may only be asserted when AUX_PWR_EN is already asserted. The MAIN_PWR_EN pin must be implemented on baseboard systems, but may optionally be used to control main power rail power supplies by the OCP NIC 3.0 card depending on the end point silicon implementation. Depending on the silicon vendor, end point devices may be able to operate in a single power domain, or may require separate power domains to function. |
|
3599 |
MAIN_PWR_EN is asserted. An OP NIC 3.0 card is allowed a max ramp time TMPL between MAIN_PWR_EN assertion and NIC_PWR_GOOD reassertion. For cards that do not have a separate AUX and MAIN power domain, this state is an unconditional transition to NIC_PWR_GOOD. |
<> |
3603 |
MAIN_PWR_EN is asserted. An OP NIC 3.0 card is allowed a max ramp time TMPL between MAIN_PWR_EN assertion and NIC_PWR_GOOD reassertion. For cards that do not have a separate Aux and Main power domain, this state is an unconditional transition to NIC_PWR_GOOD. |
|
3741 |
The Link LED shall be located on the left hand side or located on the top for each port when the OCP NIC 3.0 card is viewed in the horizontal plane. |
<> |
3745 |
The Link LED shall be located on the left-hand side or located on the top for each port when the OCP NIC 3.0 card is viewed in the horizontal plane. |
|
3743 |
For uniformity across OCP NIC 3.0 products, all link LEDs should have their luminance across the total surface area measured in millicandelas (mcd) with an average value between 12 mcd to 18 mcd. |
<> |
3747 |
For uniformity across OCP NIC 3.0 products, all link LEDs should have their luminous intensity measured in millicandelas (mcd) with an average value between 12 mcd to 18 mcd. |
|
3756 |
The activity LED shall be located on the right hand side or located on the bottom for each port when the OCP NIC 3.0 card is viewed in the horizontal plane. |
<> |
3760 |
The activity LED shall be located on the right-hand side or located on the bottom for each port when the OCP NIC 3.0 card is viewed in the horizontal plane. |
|
3758 |
For uniformity across OCP NIC 3.0 products, all activity LEDs should have their luminance across the total surface area measured in millicandelas (mcd) with an average value between 12 mcd and 18 mcd. |
<> |
3762 |
For uniformity across OCP NIC 3.0 products, all activity LEDs should have their luminous intensity measured in millicandelas (mcd) with an average value between 12 mcd and 18 mcd. |
|
3777 |
There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode (S5), and Main Power Mode (S0). These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 106 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.11. |
<> |
3781 |
There are four permissible power states for normal operation of the card: NIC Power Off, ID Mode, Aux Power Mode, and Main Power Mode. These four power states are mandatory for each OCP NIC 3.0 card. An optional fifth power state is Programming Mode and allows the FRU EEPROM to be updated in the field under the baseboard control. The normal transition order for these states is shown in Figure 106 and described in detail in the sections below. For simplicity, only the signal transitions resulting in a state change are shown. The available functions per power state are defined in Table 41. The minimum transition time between power states is defined in Section 3.11. |
|
3779 |
|
<> |
3783 |
|
|
3811 |
Aux Power Mode (S5) |
<> |
3815 |
Aux Power Mode |
|
3821 |
Main Power Mode (S0) |
<> |
3825 |
Main Power Mode |
|
3841 |
Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in ID Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 100 mV (TBD). The bleed resistor on the baseboard shall be 2.2 kΩ (TBD). If +12V_EDGE is present in ID Mode, the max usage is defined in Section 3.9. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0. |
<> |
3845 |
Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in ID Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max voltage leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 300 mV when a 1 kΩ bleed resistor is present on the baseboard. The baseboard bleed resistor is optional if the baseboard can tolerate leakage. If +12V_EDGE is present in ID Mode, the max current is defined in Section 3.9. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=0 and MAIN_PWR_EN=0. |
3842 |
Aux Power Mode (S5) |
|
3846 |
Aux Power Mode |
3843 |
The Aux Power Mode provides both +3.3V_EDGE as well as +12V_EDGE is available. +12V_EDGE in Aux mode may be used to deliver power to the OCP NIC 3.0 card, but only up to the Aux mode budget as defined in Table 42. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=0, NIC_PWR_GOOD=1 and the duration (TAPL) has passed for the ID-Aux Power Mode ramp. This guarantees the ID mode to Aux Power Mode transition (as shown in Figure 107) has completed and all Aux Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met. |
|
3847 |
The Aux Power Mode provides both +3.3V_EDGE as well as +12V_EDGE is available. +12V_EDGE in Aux mode may be used to deliver power to the OCP NIC 3.0 card, but only up to the Aux mode budget as defined in Table 42. An OCP NIC 3.0 card shall transition to this mode when AUX_PWR_EN=1, MAIN_PWR_EN=0, NIC_PWR_GOOD=1 and the duration (TAPL) has passed for the ID-Aux Power Mode ramp. This guarantees the ID mode to Aux Power Mode transition (as shown in Figure 107) has completed and all Aux Power Mode rails are within operating tolerances. The WAKE#, TEMP_WARN#, and TEMP_CRIT# bits shall not sampled until these conditions are met. |
|
|
|
3848 |
For OCP NIC 3.0, Aux Power Mode corresponds to ACPI power state S5 on the system. This could also correspond to ACPI power state S3 or S4 depending on the implementation. |
3844 |
Main Power Mode (S0) |
|
3849 |
Main Power Mode |
|
|
|
-+ |
3851 |
For OCP NIC 3.0, Main Power Mode corresponds to ACPI power state S0 on the system. This could also correspond to ACPI power state S1 depending on the implementation. |
|
3848 |
Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in Programming Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 100 mV (TBD). The bleed resistor on the baseboard shall be 2.2 kΩ (TBD). If +12V_EDGE is present in Programming Mode, the max usage is defined in Section 3.9. |
<> |
3854 |
Baseboards may disable +12V_EDGE in this power state. OCP NIC 3.0 cards are not intended to use +12V_EDGE in Programming Mode, however leakage current may be present. If +12V_EDGE is not provided by the baseboard and leakage is present, the max voltage leakage from the OCP NIC 3.0 card to the baseboard shall be limited to 300 mV when a 1 kΩ bleed resistor is present on the baseboard. The baseboard bleed resistor is optional if the baseboard can tolerate leakage. If +12V_EDGE is present in Programming Mode, the max current is defined in Section 3.9. |
|
3867 |
Aux Mode |
<> |
3873 |
Aux Power Mode |
3868 |
Main Mode |
|
3874 |
Main Power Mode |
|
3906 |
Aux Mode |
<> |
3912 |
Aux Power Mode |
3907 |
Main Mode |
|
3913 |
Main Power Mode |
|
|
|
-+ |
3969 |
|
|
|
|
-+ |
3971 |
|
|
|
|
-+ |
3973 |
|
|
4191 |
The temperature reporting interface shall be accessible in Aux Power Mode (S5), and Main Power Mode (S0). Table 51 summarizes temperature reporting requirements. These requirements improve the system thermal management and allow the baseboard management device to access key component temperatures on an OCP NIC 3.0 card. When the temperature reporting function is implemented, it is required that the temperature reporting accuracy is within ±3 °C. |
<> |
4200 |
The temperature reporting interface shall be accessible in Aux Power Mode, and Main Power Mode. Table 51 summarizes temperature reporting requirements. These requirements improve the system thermal management and allow the baseboard management device to access key component temperatures on an OCP NIC 3.0 card. When the temperature reporting function is implemented, it is required that the temperature reporting accuracy is within ±3 °C. |
|
4269 |
A pluggable transceiver module is a compact, hot-pluggable transceiver used to connect the OCP 3.0 NIC to an external physical medium. It is important for proper system operation to know the presence and temperature of pluggable transceiver modules. Table 53 summarizes pluggable module status reporting requirements. The transceiver temperature is always reported and is independent of the ASIC die temperature reporting requirements as discussed in Section 4.4. The temperature reporting interface shall be accessible in Aux Power Mode (S5), and Main Power Mode (S0). |
<> |
4278 |
A pluggable transceiver module is a compact, hot-pluggable transceiver used to connect the OCP 3.0 NIC to an external physical medium. It is important for proper system operation to know the presence and temperature of pluggable transceiver modules. Table 53 summarizes pluggable module status reporting requirements. The transceiver temperature is always reported and is independent of the ASIC die temperature reporting requirements as discussed in Section 4.4. The temperature reporting interface shall be accessible in Aux Power Mode, and Main Power Mode. |
|
4425 |
The FRU EEPROM is readable in all four power states: ID mode, Programming mode, Aux Power mode (S5), and Main Power mode (S0). |
<> |
4434 |
The FRU EEPROM is readable in all four power states: ID mode, Programming mode, Aux Power Mode, and Main Power Mode. |
|
4453 |
Card Max power (in Watts) in MAIN (S0) mode. |
<> |
4462 |
Card Max power (in Watts) in Main Power Mode. |
4454 |
The encoded value is the calculated max power of the OCP NIC 3.0 card in the Main Power (S0) mode only and does not include the consumed power by transceivers plugged into the line side receptacle(s). |
|
4463 |
The encoded value is the calculated max power of the OCP NIC 3.0 card in the Main Power Mode only and does not include the consumed power by transceivers plugged into the line side receptacle(s). |
|
4458 |
Card Max power (in Watts) in AUX (S5) mode. |
<> |
4467 |
Card Max power (in Watts) in Aux Power Mode. |
4459 |
The encoded value is the calculated max power of the OCP NIC 3.0 card in the Aux Power (S5) mode only and does not include the consumed power by transceivers plugged into the line side receptacle(s). |
|
4468 |
The encoded value is the calculated max power of the OCP NIC 3.0 card in the Aux Power Mode only and does not include the consumed power by transceivers plugged into the line side receptacle(s). |
|
4479 |
The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with active cables while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
<> |
4488 |
The encoded value represents the amount of airflow, in LFM, required to cool the card in Aux Power Mode with active cables while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
|
4481 |
0x0000-0xFFFE – LFM required for cooling card in Hot Aisle Operation.0xFFFF – Unknown. |
<> |
4490 |
0x0000 – Card only supports passive cables (e.g., Direct Attached Cables or RJ45)0x0001 – 0xFFFE – LFM required for cooling card in Hot Aisle Operation.0xFFFF – Unknown. |
|
4485 |
The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with active cables while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
<> |
4494 |
The encoded value represents the amount of airflow, in LFM, required to cool the card in Aux Power Mode with active cables while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
|
4487 |
0x0000-0xFFFE – LFM required for cooling card in Cold Aisle Operation.0xFFFF – Unknown. |
<> |
4496 |
0x0000 – Card only supports passive cables (e.g., Direct Attached Cables or RJ45)0x0001 – 0xFFFE – LFM required for cooling card in Cold Aisle Operation.0xFFFF – Unknown. |
|
4526 |
0x00 – Card only supports passive cables (e.g., RJ45)0x01 – Hot Aisle Cooling Tier 10x02 – Hot Aisle Cooling Tier 20x03 – Hot Aisle Cooling Tier 30x04 – Hot Aisle Cooling Tier 40x05 – Hot Aisle Cooling Tier 50x06 – Hot Aisle Cooling Tier 60x07 – Hot Aisle Cooling Tier 70x08 – Hot Aisle Cooling Tier 80x09 – Hot Aisle Cooling Tier 90x0A – Hot Aisle Cooling Tier 100x0B – Hot Aisle Cooling Tier 110x0C – Hot Aisle Cooling Tier 120x0D – 0xFE – Reserved 0xFF – Unknown |
<> |
4535 |
0x00 – Card only supports passive cables (e.g., Direct Attached Cables or RJ45)0x01 – Hot Aisle Cooling Tier 10x02 – Hot Aisle Cooling Tier 20x03 – Hot Aisle Cooling Tier 30x04 – Hot Aisle Cooling Tier 40x05 – Hot Aisle Cooling Tier 50x06 – Hot Aisle Cooling Tier 60x07 – Hot Aisle Cooling Tier 70x08 – Hot Aisle Cooling Tier 80x09 – Hot Aisle Cooling Tier 90x0A – Hot Aisle Cooling Tier 100x0B – Hot Aisle Cooling Tier 110x0C – Hot Aisle Cooling Tier 120x0D – 0xFE – Reserved 0xFF – Unknown |
|
4531 |
0x00 – Card only supports passive cables (e.g., RJ45)0x01 – Cold Aisle Cooling Tier 10x02 – Cold Aisle Cooling Tier 20x03 – Cold Aisle Cooling Tier 30x04 – Cold Aisle Cooling Tier 40x05 – Cold Aisle Cooling Tier 50x06 – Cold Aisle Cooling Tier 60x07 – Cold Aisle Cooling Tier 70x08 – Cold Aisle Cooling Tier 80x09 – Cold Aisle Cooling Tier 90x0A – Cold Aisle Cooling Tier 100x0B – Cold Aisle Cooling Tier 110x0C – Cold Aisle Cooling Tier 120x0D – 0xFE – Reserved 0xFF – Unknown |
<> |
4540 |
0x00 – Card only supports passive cables (e.g., Direct Attached Cables or RJ45)0x01 – Cold Aisle Cooling Tier 10x02 – Cold Aisle Cooling Tier 20x03 – Cold Aisle Cooling Tier 30x04 – Cold Aisle Cooling Tier 40x05 – Cold Aisle Cooling Tier 50x06 – Cold Aisle Cooling Tier 60x07 – Cold Aisle Cooling Tier 70x08 – Cold Aisle Cooling Tier 80x09 – Cold Aisle Cooling Tier 90x0A – Cold Aisle Cooling Tier 100x0B – Cold Aisle Cooling Tier 110x0C – Cold Aisle Cooling Tier 120x0D – 0xFE – Reserved 0xFF – Unknown |
|
4556 |
The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with passive cables or RJ45 while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
<> |
4565 |
The encoded value represents the amount of airflow, in LFM, required to cool the card in Aux Power Mode with passive cables or RJ45 while operating in a hot aisle environment with an approach air temperature of 45 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
|
4562 |
The encoded value represents the amount of airflow, in LFM, required to cool the card in AUX (S5) mode with passive cables or RJ45 while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
<> |
4571 |
The encoded value represents the amount of airflow, in LFM, required to cool the card in Aux Power Mode with passive cables or RJ45 while operating in a cold aisle environment with an approach air temperature of 35 °C. Refer to Section 6 for more information about the thermal and environmental requirements. |
|
4861 |
It is important to point out that the curves shown in Figure 120 represent only the maximum ASIC power that can be supported vs. the supplied inlet velocity. Other heat loads on the card may require airflow velocities above and beyond that required to cool the ASIC. SFP or QSFP optical transceivers located downstream of the AISC will in many cases pose a greater cooling challenge than the ASIC cooling. Cooling the optical transceivers becomes even more difficult as the ASIC power is increased due to additional preheating of the air as it moves through the ASIC heatsink. OCP NIC 3.0 designers must consider all heat sources early in the design process to ensure the card thermal solution is sufficient for the feature set. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. |
<> |
4870 |
It is important to point out that the curves shown in Figure 120 represent only the maximum ASIC power that can be supported vs. the supplied inlet velocity. Other heat loads on the card may require airflow velocities above and beyond that required to cool the ASIC. SFP or QSFP optical transceivers located downstream of the AISC will in many cases pose a greater cooling challenge than the ASIC cooling. Cooling the optical transceivers becomes even more difficult as the ASIC power is increased due to additional preheating of the air as it moves through the ASIC heatsink. OCP NIC 3.0 designers must consider all heat sources early in the design process to ensure the card thermal solution is sufficient for the feature set. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. |
|
4864 |
The server airflow capability is typically more restrictive when the OCP card is operating in standby mode (S5). The airflow available from the system cooling solution is often more restrictive due to limited power budget available in an S5 state. The graph below emphasizes that though the local OCP NIC 3.0 air temperature is typically lower than in S0 (since preheating from upstream components should be greatly reduced while in standby), the upper bound of local air velocity is a fraction of what can be generated when the system is in main power mode (S0). Card vendors must test for these conditions, making sure that the provided cooling is sufficient for both the ASIC and any installed transceivers (which will still be receiving preheat from the ASIC in S5 mode). |
<> |
4873 |
The server airflow capability is typically more restrictive when the OCP card is operating in Aux Power Mode. The airflow available from the system cooling solution is often more restrictive due to limited power budget available in Aux Power Mode. The graph below emphasizes that though the local OCP NIC 3.0 air temperature is typically lower in Main Power Mode (since preheating from upstream components should be greatly reduced while in standby), the upper bound of local air velocity is a fraction of what can be generated when the system is in Main Power Mode. Card vendors must test for these conditions, making sure that the provided cooling is sufficient for both the ASIC and any installed transceivers (which will still be receiving preheat from the ASIC in Aux Power Mode). |
4865 |
The NIC vendor shall provide the required LFM during S5 state in the FRU EEPROM (see Section 4.10.3). The cold aisle should be tested at 35 °C; the hot aisle should be tested at 45 °C. |
|
4874 |
The NIC vendor shall provide the required LFM during for Aux Power Mode in the FRU EEPROM (see Section 4.10.3). The cold aisle should be tested at 35 °C; the hot aisle should be tested at 45 °C. |
4866 |
Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in standby (S5) mode |
|
4875 |
Figure 123: Server System Airflow Capability – SFF Card Hot Aisle Cooling in Aux Power Mode |
|
4905 |
It is important to note that the supportable power for the LFF card is considerably higher than for the SFF card due to the increased size of the ASIC heatsink. In addition, optics module cooling on the LFF card will also be considerably improved due to the arrangement of the optics in parallel to the ASIC heatsink rather than in series. These thermal advantages are key drivers for the LFF card geometry. The OCP NIC 3.0 simulation was conducted within a virtual version of the LFF card test fixture defined in Section 6.4. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. |
<> |
4914 |
It is important to note that the supportable power for the LFF card is considerably higher than for the SFF card due to the increased size of the ASIC heatsink. In addition, optics module cooling on the LFF card will also be considerably improved due to the arrangement of the optics in parallel to the ASIC heatsink rather than in series. These thermal advantages are key drivers for the LFF card geometry. The OCP NIC 3.0 simulation was conducted within a virtual version of the LFF card test fixture defined in Section 6.4. In addition, OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. |
|
4913 |
Similar to Figure 122 for Hot Aisle cooling, Figure 128 below shows the ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling. |
<> |
4922 |
Similar to Figure 122 for Hot Aisle cooling, Figure 128 below shows the ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling. |
|
4920 |
Similar to Figure 128 for LFF Hot Aisle cooling, Figure 131 below shows the LFF ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including S0 (Main Power Mode) and S5 (Aux Power Mode). For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling. |
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4929 |
Similar to Figure 128 for LFF Hot Aisle cooling, Figure 131 below shows the LFF ASIC supportable power curves with an overlay of three Cold Aisle server airflow capability ranges. Designers must ensure that their thermal solutions and resulting card airflow requirements fall within the range of supportable Cold Aisle system airflow velocity. Cards that are under-designed (e.g., require airflow greater than the system capability) will have thermal issues when deployed into the server system. Similar to the Hot Aisle cases, cooling of the optical transceivers need to be taken into consideration even though they are not preheated by the ASIC in the Cold Aisle case. OCP NIC 3.0 designers must consider all power modes in the design process – including Main Power Mode and Aux Power Mode. For both modes, the card designer must provide the airflow requirements in the OEM FRU record as described in Section 4.10.3. Card designers are advised to work closely with system vendors to ensure they target the appropriate airflow and temperature boundary conditions for both Hot and Cold Aisle cooling. |
|
|
|
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4974 |
When measuring the cold aisle inlet temperature, a separate thermocouple in front of the faceplate should be used instead of using the candlestick sensors on-board the thermal test fixture. The thermocouple should be centered on the faceplate area and placed 25 ±2 mm away from the surface. This method is more representative of the cold aisle inlet temperature compared to using the on-board thermal-test fixture candlestick sensors which may be affected by the heat dissipated from the ASIC. |
|
|
|
4975 |
Figure 140: External Thermocouple Placement for Cold Aisle Inlet Temperature Measurement |
4965 |
Figure 140 and Figure 141 below show the air velocity at each sensor location vs. the total fixture flow rate in CFM. The curves shown in these figures are based on the data collected from the CFD models discussed in Section 6.3. Note the error between the velocities obtained from the sensor locations vs. the velocity based on the duct cross-sectional area. |
|
4976 |
Figure 141 and Figure 142 below show the air velocity at each sensor location vs. the total fixture flow rate in CFM. The curves shown in these figures are based on the data collected from the CFD models discussed in Section 6.3. Note the error between the velocities obtained from the sensor locations vs. the velocity based on the duct cross-sectional area. |
4966 |
Figure 140: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow |
|
4977 |
Figure 141: SFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow |
4967 |
Figure 141: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow |
|
4978 |
Figure 142: LFF Fixture, Hot Aisle Flow – Candlestick Air Velocity vs. Volume Flow |
|
4975 |
A graphical view of the Card Cooling Tiers is shown in Figure 142. The Tiers range from 0 LFM to as high as 1000 LFM at 55 °C local inlet temperature. It is important to understand that the cooling tiers extend well beyond the airflow range of most server systems. As noted in Section 6.2, card designers must consider the airflow capability of the systems that the cards are to be used in when designing the card thermal solution and component placement. Figure 143 and Figure 144 below show the range of typical system capability for Hot Aisle and Cold Aisle configurations. Cards designed to these typical ranges (Tiers 1-6) will be low risk to support in most if not all server systems. Alternatively, cards that require Tier 7 or greater may still work in many server systems but may require extra validation testing, specific system slot location requirements, and potentially ambient temperature and hardware restrictions. |
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4986 |
A graphical view of the Card Cooling Tiers is shown in Figure 143. The Tiers range from 0 LFM to as high as 1000 LFM at 55 °C local inlet temperature. It is important to understand that the cooling tiers extend well beyond the airflow range of most server systems. As noted in Section 6.2, card designers must consider the airflow capability of the systems that the cards are to be used in when designing the card thermal solution and component placement. Figure 144 and Figure 145 below show the range of typical system capability for Hot Aisle and Cold Aisle configurations. Cards designed to these typical ranges (Tiers 1-6) will be low risk to support in most if not all server systems. Alternatively, cards that require Tier 7 or greater may still work in many server systems but may require extra validation testing, specific system slot location requirements, and potentially ambient temperature and hardware restrictions. |
4976 |
Figure 142: Graphical View of Card Cooling Tiers |
|
4987 |
Figure 143: Graphical View of Card Cooling Tiers |
4977 |
Figure 143: Typical Operating Range for Hot Aisle Configurations |
|
4988 |
Figure 144: Typical Operating Range for Hot Aisle Configurations |
4978 |
Figure 144: Typical Operating Range for Cold Aisle Configurations |
|
4989 |
Figure 145: Typical Operating Range for Cold Aisle Configurations |
|
4984 |
The fixture is comprised of a universal baseplate that allows for attaching SFF or LFF rail guides and simulated chassis faceplates. The baseplate includes an industry standard vibration table hole pattern for securing the UUT for test. Figure 145 and Figure 146 show the SFF and LFF fixtures, respectively. |
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4995 |
The fixture is comprised of a universal baseplate that allows for attaching SFF or LFF rail guides and simulated chassis faceplates. The baseplate includes an industry standard vibration table hole pattern for securing the UUT for test. Figure 146 and Figure 147 show the SFF and LFF fixtures, respectively. |
|
4986 |
Figure 145: SFF Shock and Vibe Fixture |
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4997 |
Figure 146: SFF Shock and Vibe Fixture |
4987 |
Figure 146: LFF Shock and Vibe Fixture |
|
4998 |
Figure 147: LFF Shock and Vibe Fixture |
|
5024 |
Figure 147: Dye and Pull Type Locations |
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5035 |
Figure 148: Dye and Pull Type Locations |
|
5026 |
Dye coverage of >50% (“D” and “E” in Figure 148) of any Type 2 or Type 3 BGA cracks are present in the test sample. |
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5037 |
Dye coverage of >50% (“D” and “E” in Figure 149) of any Type 2 or Type 3 BGA cracks are present in the test sample. |
|
5028 |
Figure 148: Dye Coverage Percentage |
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5039 |
Figure 149: Dye Coverage Percentage |
|
5097 |
EN 55024 may alternatively be reported. Required ±4 kV contact charge and ±8 kV air discharge. |
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5108 |
EN 55024 may alternatively be reported. Required ±4 kV contact discharge and ±8 kV air discharge. |
|
5101 |
Required ±8 kV contact charge and ±15 kV air discharge with interruptions not greater than 2 seconds. The device shall self-recover without operator intervention. |
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5112 |
Required ±8 kV contact discharge and ±15 kV air discharge with interruptions not greater than 2 seconds. The device shall self-recover without operator intervention. |
|
5131 |
- Change NC-SI over RBT RXD/TXD pins to a pull-up instead of a pull down.- Update power sequencing diagram. REFCLK is disabled before silicon transitions to AUX Power Mode. |
<> |
5142 |
- Change NC-SI over RBT RXD/TXD pins to a pull-up instead of a pull down.- Update power sequencing diagram. REFCLK is disabled before silicon transitions to Aux Power Mode. |
|
5171 |
- Section 3.9.x – Clarified ID-Aux and Aux-Main Power Mode transition requirements to prevent sampling health status pins until cards have fully entered into Aux and Main modes to prevent false indication. |
<> |
5182 |
- Section 3.9.x – Clarified ID-Aux and Aux-Main Power Mode transition requirements to prevent sampling health status pins until cards have fully entered into Aux and Main Power Modes to prevent false indication. |
|
5246 |
- Sections 6.2.x – Add notes to consider airflow requirements in Aux and Main power modes for SFF & LFF in Hot & Cold Aisle implementations. |
<> |
5257 |
- Sections 6.2.x – Add notes to consider airflow requirements in Aux and Main Power Modes for SFF & LFF in Hot & Cold Aisle implementations. |
|
|
|
-+ |
5341 |
- General – Uniformly changed references for Aux Power Mode and Main Power Mode. Removed references to ACPI power states S5 and S0. Added additional text to Section 3.8.3 and 3.8.4 for the included ACPI power states. |
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<> |
5345 |
- Section 2.5.1, 2.5.2 – Figure 24 & 29 - Update PCB break off note #3 to include feature max tolerances.- Section 2.8.2 – Figure 40 – Updated dimension notation with parenthesis and add center line labeled as CL DATUM H for consistency across form-factor figures. |
5333 |
- Section 2.5.1, 2.5.2 – Update PCB break off note #3 to include feature max tolerances. |
|
5346 |
- Section 2.8.3 – Figure 43 – Add center line labeled as CL DATUM H for consistency across form-factor figures. |
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|
|
5347 |
- Section 2.8.4 – Figure 46 – Add center line labeled as CL DATUM H for consistency across form-factor figures. |
|
|
|
5348 |
- Section 3. 4 – Add clarification statement for Aux Power Mode and Main Power Mode in relation to ACPI power states. |
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|
|
<> |
5353 |
- Section 3.8.3 – Clarified that Aux Power Mode includes ACPI power states S3, S4 and S5 as they are equivalent from a power delivery and sequencing perspective. |
5338 |
- Section 3.8.2, 3.8.5 – Clarifications to +12V_EDGE in ID/Programming mode. +12V_EDGE is now marked as optional in these two states. A max permissible leakage voltage is stated and the baseboard requires a bleed resistor. |
|
5354 |
- Section 3.8.2, 3.8.5 – Clarifications to +12V_EDGE in ID/Programming mode. +12V_EDGE is now marked as optional in these two states. A max permissible leakage voltage is stated and the baseboard has an optional a bleed resistor. |
|
5345 |
Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. |
<> |
5361 |
Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19. |
5346 |
Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. |
|
5362 |
Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19. |
|
|
|
-+ |
5368 |
- Section 6.4.4 – Add thermocouple notes for cold-aisle inlet temperature measurements. |
|
|
|
5369 |
1.0.9 |
|
|
|
5370 |
10/28/2020 |
|
|
|
5371 |
OCP NIC 3.0 Subgroup |
|
|
|
5372 |
Document release - version R1.1.0 |
|
5353 |
09/15/2020 |
<> |
5374 |
10/xx/2020 |
|
5363 |
- Offset 4, 5 – Clarified that the Card Max Power in Main mode and the Card Max Power in Aux Mode do not include the power consumed by transceivers plugged into the line side receptacle(s). |
<> |
5384 |
- Offset 4, 5 – Clarified that the Card Max Power in Main Power Mode and the Card Max Power in Aux Power Mode do not include the power consumed by transceivers plugged into the line side receptacle(s). |
|
5407 |
- Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. |
<> |
5428 |
- Offset 9 – Clarified this is the Hot aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19. |
5408 |
- Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. |
|
5429 |
- Offset 11 – Clarified this is the Cold aisle standby air flow requirements when using active cables. Defined value 0x0000 for card only supporting passive cables - similar to offset 19. |